IDT74LVC07A
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS HEX
BUFFER/DRIVER WITH
OPEN-DRAIN OUTPUTS
AND 5 VOLT TOLERANT I/O
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages
IDT74LVC07A
FEATURES:
DESCRIPTION:
This hex buffer/driver is built using advanced dual metal CMOS technol-
ogy. The outputs of the LVC07A device are open-drain and can be
connected to other open-drain outputs to implement active-low wired-OR or
active-high wired-AND functions. The maximum sink current is 24mA.
The LVC07A has been designed with a +24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 2.5V, 3.3V (LVTTL), or 5V (CMOS)
devices. This feature allows the use of this device as a translator in a mixed-
system environment.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1
A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
6
A
6
Y
5
A
5
Y
4
A
4
Y
A
Y
1
Y
2
A
2
Y
3
A
3
Y
GND
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xA
xY
Data Inputs
Data Outputs
Description
FUNCTION TABLE
(EACH BUFFER/DRIVER)
(1)
Inputs
xA
H
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Outputs (with pull-up)
xY
H
L
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2000 Integrated Device Technology, Inc.
JULY 2000
DSC-4723/1
IDT74LVC07A
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
Max
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
Unit
V
°C
mA
mA
mA
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
Parameter
V
CC
= 2.3V to 2.7V
Input HIGH Voltage Level
V
CC
= 2.7V to 3.6V
V
CC
= 4.5V to 5.5V
V
CC
= 2.3V to 2.7V
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V, V
IN
= GND or V
CC
—
—
—
—
—
–0.7
100
—
±50
–1.2
—
10
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.7V to 3.6V
V
CC
= 4.5V to 5.5V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
0.7 x V
CC
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
Max.
—
—
—
0.7
0.8
0.3 x V
CC
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
—
—
500
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2
IDT74LVC07A
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OL
Parameter
Output LOW Voltage
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Min.
—
—
—
—
—
Max.
0.2
0.4
0.7
0.4
0.55
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V±0.2V
Symbol
C
PD
Parameter
Power Dissipation Capacitance per Buffer/Driver
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
2.5
V
CC
= 3.3V±0.3V
Typical
4
V
CC
= 5V±0.5V
Typical
7
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V±0.2V
Symbol
t
PZL
t
PLZ
t
SK
(o)
Output Skew
(2)
—
—
—
—
—
—
—
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
V
CC
= 2.7V
Min.
1
Max.
3.3
V
CC
= 3.3V ± 0.3V
Min.
1
Max.
2.9
V
CC
= 5V±0.5V
Min.
1
Max.
2.6
Unit
ns
Parameter
xA to xY
Min.
1
Max.
2.8
3
IDT74LVC07A
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
V
CC(2)
=3.3V±0.3V & 2.7V
6
2.7
1.5
300
300
50
V
CC(2)
= 5V±0.5V
2 x Vcc
3
1.5
200
200
50
V
V
V
mV
mV
pF
Unit
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
Propagation Delay
LVC QUAD Link
V
CC
500Ω
Pulse
Generator
(1, 2)
V
LOAD
Open
GND
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
LVC QUAD Link
V
IN
D.U.T.
R
T
V
OUT
500Ω
C
L
LVC QUAD Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test
t
PZL
t
PLZ
t
PHZ
t
PZH
Switch
V
LOAD
DATA
INPUT
TIMING
INPUT
SYNCHRONOUS
CONTROL
ASYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC QUAD Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
OUTPUT 2
t
PLH2
t
PHL2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC QUAD Link
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
Output Skew - t
SK
(
X
)
Pulse Width
4
IDT74LVC07A
3.3V CMOS HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
LVC XXX
XX
IDT
Temp. Range
Device Type Package
DC
PY
PG
07A
74
Small Outline IC
Shrink Small Outline Package
Thin Shrink Small Outline Package
Hex Buffer/Driver with Open Drain Outputs, +24mA
– 40°C to +85°C
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logichelp@idt.com
(408) 654-6459
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