CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle)
output current must not exceed 30mA for maximum reliability.
Electrical Specifications
V
SUPPLY
=
±5V,
A
V
= +2, R
F
= 250Ω, R
L
= 100Ω, Unless Otherwise Specified
(NOTE 3)
TEST
LEVEL
TEMP.
(
o
C)
PARAMETER
INPUT CHARACTERISTICS
Input Offset Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNITS
A
A
25
Full
Full
25
Full
25
Full
25
Full
Full
25
Full
25
Full
Full
25
Full
25
Full
25, 85
-40
25
25
-
-
-
47
45
50
47
-
-
-
-
-
-
-
-
-
-
-
-
0.8
0.5
-
-
1
2
10
50
48
53
51
4
5
30
0.5
0.5
2
3
40
3
3
1.6
1.6
1.7
1.4
60
1.6
5
8
-
-
-
-
-
10
15
-
1
3
10
15
-
6
8
5
8
-
-
-
-
mV
mV
µV/
o
C
dB
dB
dB
dB
µA
µA
nA/
o
C
µA/V
µA/V
µA
µA
nA/
o
C
µA/V
µA/V
µA/V
µA/V
MΩ
MΩ
Ω
pF
Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio
Input Offset Voltage
Power Supply Rejection Ratio
Non-Inverting Input Bias Current
∆V
CM
=
±2V
∆V
CM
=
±2V
∆V
PS
=
±1.25V
∆V
PS
=
±1.25V
B
A
A
A
A
A
A
Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity
Inverting Input Bias Current
∆V
PS
=
±1.25V
∆V
PS
=
±1.25V
B
A
A
A
A
Inverting Input Bias Current Drift
Inverting Input Bias Current
Common-Mode Sensitivity
Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance
∆V
CM
=
±2V
∆V
CM
=
±2V
∆V
PS
=
±1.25V
∆V
PS
=
±1.25V
∆V
CM
=
±2V
∆V
CM
=
±2V
Inverting Input Resistance
Input Capacitance
B
A
A
A
A
A
A
B
B
2
HFA1109
Electrical Specifications
V
SUPPLY
=
±5V,
A
V
= +2, R
F
= 250Ω, R
L
= 100Ω, Unless Otherwise Specified
(Continued)
(NOTE 3)
TEST
LEVEL
A
TEMP.
(
o
C)
Full
PARAMETER
Input Voltage Common Mode Range
(Implied by V
IO
CMRR, +R
IN
, and -I
BIAS
CMS tests)
Input Noise Voltage Density (Note 4)
Non-Inverting Input Noise Current Density
(Note 4)
Inverting Input Noise Current Density
(Note 4)
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain (Note 4)
Minimum Stable Gain
AC CHARACTERISTICS
-3dB Bandwidth
(V
OUT
= 0.2V
P-P
, Note 4)
TEST CONDITIONS
MIN
±2
TYP
±2.5
MAX
-
UNITS
V
f = 100kHz
f = 100kHz
f = 100kHz
B
B
B
25
25
25
-
-
-
4
2.4
40
-
-
-
nV/√Hz
pA/√Hz
pA/√Hz
B
B
25
Full
-
-
500
1
-
-
kΩ
V/V
A
V
= -1, R
F
= 200Ω
B
B
25
Full
25
Full
25
Full
25
Full
25
Full
25
Full
25
Full
25
Full
25
Full
25
Full
300
290
280
260
390
350
-
-
-1.0
-1.1
-1.6
-1.7
-1.9
-2.2
±0.3
±0.4
±0.8
±0.9
±1.3
±1.4
375
360
330
320
450
410
0
0
-0.45
-0.45
-0.75
-0.75
-0.85
-0.85
±0.1
±0.1
±0.35
±0.35
±0.6
±0.6
-
-
-
-
-
-
0.2
0.5
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
A
V
= +1, +R
S
= 550Ω (PDIP),
+R
S
= 700Ω (SOIC)
A
V
= +2
B
B
B
B
Gain Peaking
A
V
= +2, V
OUT
= 0.2V
P-P
B
B
Gain Flatness
(A
V
= +2, V
OUT
= 0.2V
P-P
, Note 4)
To 125MHz
B
B
To 200MHz
B
B
To 250MHz
B
B
Gain Flatness
(A
V
= +1, +R
S
= 550Ω (PDIP),
+R
S
= 700Ω (SOIC), V
OUT
= 0.2V
P-P
,
Note 4)
To 125MHz
B
B
To 200MHz
B
B
To 250MHz
B
B
OUTPUT CHARACTERISTICS
Output Voltage Swing, Unloaded
(Note 4)
Output Current
(Note 4)
Output Short Circuit Current
Closed Loop Output Resistance (Note 4)
Second Harmonic Distortion
(V
OUT
= 2V
P-P
, Note 4)
A
V
= -1, R
L
=
∞
A
A
A
V
= -1, R
L
= 75Ω
A
A
A
V
= -1
DC, A
V
= +1
20MHz
60MHz
B
B
B
B
25
Full
25, 85
-40
25
25
25
25
±3
±2.8
±33
±30
-
-
-
-
±3.2
±3
±36
±33
120
0.05
-55
-57
-
-
-
-
-
-
-
-
V
V
mA
mA
mA
Ω
dBc
dBc
3
HFA1109
Electrical Specifications
V
SUPPLY
=
±5V,
A
V
= +2, R
F
= 250Ω, R
L
= 100Ω, Unless Otherwise Specified
(Continued)
(NOTE 3)
TEST
LEVEL
B
B
B
TEMP.
(
o
C)
25
25
25
PARAMETER
Third Harmonic Distortion
(V
OUT
= 2V
P-P
, Note 4)
Reverse Isolation (S
12
)
TRANSIENT CHARACTERISTICS
Rise and Fall Times
TEST CONDITIONS
20MHz
60MHz
30MHz
MIN
-
-
-
TYP
-68
-60
-65
MAX
-
-
-
UNITS
dBc
dBc
dB
V
OUT
= 0.5V
P-P
B
B
25
Full
25
Full
25
Full
25
Full
25
Full
25
25
25
25
-
-
-
-
2300
2200
475
430
940
800
-
-
-
-
1.1
1.1
0
0.5
2600
2500
550
500
1100
950
19
23
36
5
1.3
1.4
2
5
-
-
-
-
-
-
-
-
-
-
ns
ns
%
%
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
ns
ns
ns
ns
Overshoot
V
OUT
= 0.5V
P-P
B
B
Slew Rate
A
V
= -1, R
F
= 200Ω
V
OUT
= 5V
P-P
A
V
= +1, V
OUT
= 4V
P-P
,
+R
S
= 550Ω (PDIP),
+R
S
= 700Ω (SOIC)
A
V
= +2, V
OUT
= 5V
P-P
B
B
B
B
B
B
Settling Time
(V
OUT
= +2V to 0V step, Note 4)
To 0.1%
To 0.05%
To 0.01%
B
B
B
B
Overdrive Recovery Time
VIDEO CHARACTERISTICS
Differential Gain
(f = 3.58MHz)
V
IN
=
±2V
R
L
= 150Ω
B
B
25
Full
25
Full
25
Full
25
Full
-
-
-
-
-
-
-
-
0.02
0.03
0.04
0.05
0.02
0.02
0.05
0.06
0.06
0.09
0.09
0.12
0.06
0.06
0.09
0.13
%
%
%
%
Degrees
Degrees
Degrees
Degrees
R
L
= 75Ω
B
B
Differential Phase
(f = 3.58MHz)
R
L
= 150Ω
B
B
R
L
= 75Ω
B
B
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Power Supply Current (Note 4)
C
A
A
NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See Typical Performance Curves for more information.
25
25
Full
±4.5
-
-
-
9.6
10
±5.5
10
11
V
mA
mA
4
HFA1109
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth depen-
dency on closed loop gain isn’t as severe as that of a voltage
feedback amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier’s
unique relationship between bandwidth and R
F
. All current
feedback amplifiers require a feedback resistor, even for
unity gain applications, and R
F
, in conjunction with the inter-
nal compensation capacitor, sets the dominant pole of the
frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to R
F
. The HFA1109 design is opti-
mized for a 250Ω R
F
at a gain of +2. Decreasing R
F
decreases stability, resulting in excessive peaking and over-
shoot (Note: Capacitive feedback will cause the same prob-
lems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
R
F
can be decreased in a trade-off of stability for bandwidth.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN (A
CL
)
-1
+1
+2
+5
+10
R
F
(Ω)
200
250 (+
R
S
= 550Ω) PDIP
250 (+
R
S
= 700Ω) SOIC
250
100
90
BANDWIDTH (MHz)
400
350
50Ω
510Ω
1
2
3
4
10µF
0.1µF
-5V
GND
510Ω
V
H
8
7
50Ω
IN
6
5
GND
OUT
V
L
0.1µF
10µF
+5V
ble oscillations. In most cases, the oscillation can be avoided
by placing a resistor (R
S
) in series with the output prior to
the capacitance.
R
S
and C
L
form a low pass network at the output, thus limit-
ing system bandwidth well below the amplifier bandwidth. By
decreasing R
S
as C
L
increases, the maximum bandwidth is
obtained without sacrificing stability. In spite of this, band-
width still decreases as the load capacitance increases.
Evaluation Board
The performance of the HFA1109 may be evaluated using
the
HFA11XX
evaluation
board
(part
number
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier, the two 510Ω
gain setting resistors on the evaluation board should be
changed to 250Ω.
The layout and schematic of the board are shown in Figure 1.
.
BOARD SCHEMATIC
450
160
70
Table 1 lists recommended R
F
values, and the expected
bandwidth, for various closed loop gains. For a gain of +1, a
resistor (
+
R
S
) in series with +IN is required to reduce gain
peaking and increase stability
TOP LAYOUT
PC Board Layout
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board.
The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid ground
plane is a must!
Attention should be given to decoupling the
power supplies. A large value (10µF) tantalum in parallel with a
small value (0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to ground
seen by the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. Thus it is recommended that
the ground plane be removed under traces connected to -IN,
and connections to -IN should be kept as short as possible.
1
+IN
V
H
OUT V+
V
L
V-
GND
BOTTOM LAYOUT
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly ter-
minated transmission line will degrade the amplifier’s phase
margin resulting in frequency response peaking and possi-
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