IDT821024
Non-Programmable Quad PCM CODEC
Preliminary Data Sheet, December 2000 (Ver 1.0)
File No. IDT821024DS(L)
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Features
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Description
The IDT821024 is a single-chip, four channel PCM CODEC
with on-chip filters. The device provides both
µ-law
and A-
law companding digital-to-analog and analog-to-digital
conversions based on ITU-T G.711 - G.714 specifications. It
also provides the two-to-four wire conversion function (the
external balance impedance required). The digital filters in
IDT821024 provides the necessary transmit and receive filtering
for voice telephone circuit to interface with time-division
multiplexed systems. All of the digital filters are performed in
digital signal processors operating from an internal clock, which
is derived from MCLK. The fixed filters set the transmit and
receive gain and frequency response.
In IDT821024, the PCM data is read and written to the PCM
highway in time slots determined by the individual Frame
Sync signals (FSR
n
and FSX
n
, where n = 1−4) at rates from
256 KHz to 8.192 MHz. Both Long and Short Frame Sync
modes are available in the device.
The IDT821024 can be used in digital telecommunication
applications such as PBX, Central Office Switch, Digital
Telephone and Integrated Voice/Data Access Unit.
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♦
♦
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♦
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4 channel CODEC with on-chip filters
Selectable A-law or
µ-law
companding
Master clock frequency selection: 2.048 MHz, 4.096
MHz or 8.192 MHz
−
Internal timing automatically adjusted based on
MCLK and frame sync signal
Separate PCM and master clock
Single PCM port with up to 8.192 MHz operation (128
channels)
Transhybrid balance impedance hardware
programmable via external components
Transmit gains hardware programmable via external
components
Low power +5.0 V CMOS technology
+5.0 V single power supply
Instant recovery after audio reception/transmission
interrupted by spurious transient states
.
Package available:
IDT821024-XL
32 pin PLCC
IIN1
VOUT1
IIN2
VOUT2
IIN3
VOUT3
IIN4
VOUT4
Analog Front End
Ch1
Analog Front End
Ch2
Analog Front End
Ch3
Analog Front End
Ch4
PCM TSA 1
PCM TSA 2
FSX1
FSR1
FSX2
FSR2
FSX3
FSR3
FSX4
FSR4
DX
TSC
DR
PCLK
DSP
PCM TSA 3
PCM TSA 4
PCM
Interface
MCLK
IREF
CNF
Clock
&
Reference Circuits
Control
PDN1~4
A/µ
AGND
Figure-1. Block Diagram
Integrated Device Technology, Inc.
DGND
VCCA
VCCD
IDT821024
Non-Programmable Quad PCM CODEC
Pin Connection
VOUT1
32
31
30
4
3
2
1
MCLK
PDN1
PDN2
PDN3
PDN4
CNF
IIN1
IIN2
VOUT2
VCCA
IREF
AGND
VOUT3
IIN3
IIN4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
29
28
27
26
PCLK
TSC
DGND
DX
VCCD
DR
FSR1
FSX1
FSR2
32-Pin
PLCC
25
24
23
22
20
13
21
VOUT4
A/µ
µ
FSX4
FSR4
FSX3
FSR3
Figure-2. Pin Assignment
Page-2
FSX2
IDT821024
Non-Programmble Quad PCM CODEC
Pin Description
Name
AGND
VCCA
Type
--
--
Pin Number
10
8
Description
Analog Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Analog Power Supply.
All power supply pins should be connected to the power plane of the circuit
board.
Digital Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Digital Power Supply.
All power supply pins should be connected to the power plane of the circuit
board.
Receive PCM Data Input.
The PCM data for Channels 1, 2, 3 and 4 is shifted serially into DR pin during
the time slot determined by the Receive Frame Sync Signal (FSR) with MSB
first. A byte of data for each channel is received every 125
µs
at the PCLK
rate.
Transmit PCM Data Output.
The PCM data for Channels 1, 2, 3 and 4 is shifted serially out of DX pin
during the time slot determined by the Transmit Frame Sync Signal (FSX) with
MSB first. A byte of data for each channel is transmitted every 125
µs
at the
PCLK rate. DX is high impedance between time slots.
Receive Frame Sync Input for Channel 1/2/3/4
This 8kHz signal pulse identifies the receive time slot for Channel N on a
system’s receive PCM frame. It must be synchronized to PCLK.
Transmit Frame Sync Input for Channel 1/2/3/4
This 8 kHz signal pulse identifies the transmit time slot for Channel N on a
system’s transmit PCM frame. It must be synchronized to PCLK.
Reference Current.
The IREF1 output is biased at the internal reference voltage.
Voice Frequency Receiver Output for Channel 1/2/3/4
This is the output of receiver power amplifier for Channel N. The received
digital data at DRA is processed and converted to an analog signal at this pin.
Voice Frequency Transmitter Input for Channel 1/2/3/4
This is the input to the gain setting amplifier in the transmit path for Channel N.
The analog voice band voltage signal is applied to this pin through a resistor.
This input is a virtual AC ground input which is biased at the IREF1 pin. The
audio signal is processed and converted into an digital signal for DXA.
Master Clock.
The Master Clock provides the clock for DSP. It can be either 2.048 MHz or
4.096 MHz. The device determines the MCLK frequency by the FSX inputs
and makes the necessary internal adjustments automatically. The MCLK must
be an integer multiple of the FSX frequency.
PCM Clock.
The PCM Clock shifts out PCM data from DXA pin and shifts in PCM data on
DRA pin. It is an integer multiple of the frame sync frequency. When PCLK is
connected with MCLK, it can generate the DSP clock as well.
Time Slot Control.
This open drain output is low active. When PCM data is transmitted on DXA
pin for any of the four channels, this pin will be pulled low.
DGND
VCCD
--
--
27
25
DR
I
24
DX
O
26
FSR1
FSR2
FSR3
FSR4
FSX1
FSX2
FSX3
FSX4
IREF
VOUT1
VOUT2
VOUT3
VOUT4
I1IN1
I1IN2
I1IN3
I1IN4
MCLK
I
I
O
O
23
21
19
17
22
20
18
16
9
4
7
11
14
5
6
12
13
30
I
I
PCLK
I
29
TSC
O
28
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IDT821024
Non-Programmable Quad PCM CODEC
Pin Description(continued)
Name
A/µ
Type
I
Pin Number
15
Description
A/µ-Law Selection.
When this pin is low,
µ-Law
is selected; when this pin is high, A-Law is
selected. This pin can be connected to VCCD or DGND pin directly.
Channel 1/2/3/4 Power Down.
When this pin is high, Channel N is powered down.
PDN1
PDN2
PDN3
PDN4
CNF
I
O
2
1
32
31
3
Capacitor For Noise Filter.
This pin should be connected to AGND via a 0.1µF capacitor.
Page-4
IDT821024
Non-Programmble Quad PCM CODEC
Functional Description
The IDT821024 contains four channel PCM CODEC with on
chip digital filters. It provides the four-wire solution for the
subscriber line circuitry in digital switches. The device
converts analog voice signal into digital PCM samples, and
converts digital PCM samples back into analog signal.
Digital filters are used to bandlimit the voice signals during
conversion. Either A-law or
µ-law
is supported by IDT821024,
and the law selection is performed by A/µ pin.
The frequency of the master clock (MCLK) can be 2.048
MHz, 4.096 MHz, or 8.192 MHz. Internal circuitry determines
the master clock frequency automatically.
Four channels of serial PCM data are time multiplexed via
two pins, DX and DR. The time slots of the four channels
are determined by the individual Frame Sync signals at rates
from 256 kHz to 8.192 MHz. For each channel, the IDT821024
provides a transmit and receive Frame Sync input.
The IDT821024 can be powered down on a per-channel basis
to save power consumption. Channel Power Down Pins
PDN1-4 configures channels to be active (power-on) or
standby (power-down) specificly.
Operation Control
The following operation description applies to all four channels
of the IDT821024.
Power-on Sequence and Master Clock Configuration
To power on IDT821024, users should follow this sequence:
1. Apply ground;
2. Apply VCC, finish signal connections;
3. Set PDN1-4 pins high, thus all of the 4 channels are
powered down;
The master clock (MCLK) frequency of IDT821024 can be
configured as 2.048 MHz, 4.096 MHz and 8.192 MHz. Using
the Transmit Frame Sync (FSX) inputs, the device
determines the MCLK frequency and makes the necessary
internal adjustments automatically. The MCLK frequency
must be an interger multiple of the Frame Sync frequency.
Operating Modes
There are two operating modes for each transmit or receive
channel: standby mode (when the channel is powered
down) and normal mode (when the channel is powered
on). In standby mode, all circuits are powered down with
the analog outputs placed in high impedance state.
Each of the four channels in the IDT821024 can be in either
normal mode or standby mode. The mode selection of each
channel is done by its corresponding PDN pin. When PDNn
is 1, Channel N is in standby mode; when PDNn is 0,
Channel N is in normal mode.When in normal mode, each
channel of the IDT821024 is able to transmit and receive both
PCM and analog information. This is the operating mode
when a telephone call is in progress.
Companding Law Selection
A device pin A/µ is provided by IDT821024 for the companding
law selection. When the pin is low,
µ-law
is selected; when
the pin is high, A-law is selected.
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