3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
512 x 512
.EATURES:
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IDT72V70200
512 x 512 channel non-blocking switching at 2.048 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS
®
/GCI interfaces
Accept 16 serial data streams of 2.048 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
Available in 84-pin Plastic Leaded Chip Carrier (PLCC),
•
•
100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack
(PQFP) and 100-pin Thin Quad Flatpack (TQFP)
3.3V Power Supply
Operating Temperature Range -40°C to +85°C
°
°
DESCRIPTION:
The IDT72V70200 is a non-blocking digital switch that has a capacity of
512 x 512 channels at 2.048 Mb/s. Some of the main features are: program-
mable stream and channel control, Processor Mode, input offset delay and high-
impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
.UNCTIONAL BLOCK DIAGRAM
V
CC
GND
RESET
TMS
TDI
TDO
TCK
TRST
IC
ODE
Test Port
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
Loopback
Receive
Serial Data
Streams
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
Timing Unit
Microprocessor Interface
CLK
F0i
FE
IC
AS/ IM DS/
RD
ALE
CS
R/W/ A0-A7
DTA
D8-D15/
WR
AD0-AD7
CCO
5711 drw01
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc.
AUGUST 2001
1
DSC-5711/3
2001
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
12
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
GND
Vcc
TX0-15
(1)
RX0-15
(1)
F0i
(1)
FE
(1)
CLK
(1)
TMS
TDI
TDO
TCK
(1)
TRST
NAME
Ground.
Vcc
TX Output 0 to 15
(Three-state Outputs)
RX Input 0 to 15
Frame Pulse
Frame Evaluation
Clock
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
I/O
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
Serial data output stream. These streams have a data rate of 2.048 Mb/s.
Serial data input stream. These streams have a data rate of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS
®
and GCI specifications.
This pin is the frame measurement input.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). This input accepts a 4.096 MHz clock.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
Provides the clock to the JTAG test logic.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70200 is in the normal functional mode.
O
I
I
I
I
I
I
O
I
I
IC
(1)
RESET
(1)
Internal Connection
Device Reset
(Schmitt Trigger Input)
I
I
Connect to GND for normal operation. This pin must be LOW for the IDT72V70200 to function normally and to
comply with IEEE 1114 (JTAG) boundary scan requirements.
This input (active LOW) puts the IDT72V70200 in its reset state that clears the device internal counters, registers
and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET
pin must be held LOW for a minimum of 100ns to reset the device.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS.
This active LOW input works in conjunction with
CS
to enable the read and write operations. For Intel multiplexed
bus operation, this input is
RD.
This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is
WR.
This active LOW input is used with
RD
to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70200.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
bus operation, connect this pin to ground.
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is a 4.096 Mb/s output containing 512 bits per frame respectively. The level of each bit is determined by
the CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
A0-7
(1)
DS/RD
(1)
Address 0-7
Data Strobe/Read
I
I
R/W /
WR
(1)
Read/Write / Write
I
CS
(1)
AS/ALE
(1)
IM
(1)
AD0-7
(1)
D8-15
(1)
DTA
(1)
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
I
I
I
Address/Data Bus 0 to 7 I/O
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
I/O
O
CCO
(1)
ODE
(1)
O
I
NOTE:
1. These pins are 5V tolerant.
4
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
12
COMMERCIAL TEMPERATURE RANGE
.UNCTIONAL DESCRIPTION
The IDT72V70200 is capable of switching 512 x 512, 64 Kbit/s PCM or
N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT72V70200 can have a bit rate of
2.048 Mb/s and are arranged in 125µs wide frames, which contain 32 channels
respectively. The data rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output time-
slots on a per channel basis allowing for transfer of control and status information.
The IDT72V70200 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS
®
or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70200 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame offset
delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 8.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70200 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 512 bytes.
Data to be output on the serial streams (TX0-15) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all output
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferred to the parallel-to-serial converters and then onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
on the TX streams in every frame until the data is changed by the microprocessor.
As the IDT72V70200 can be used in a wide variety of applications, the device
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70200 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
®
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
The input 8 KHz frame pulse can be in either ST-BUS
®
or GCI format. The
IDT72V70200 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
format, every second falling
edge of the master clock marks a bit boundary and the data is clocked in on the
rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In
GCI format, every second rising edge of the master clock marks the bit boundary
and data is clocked in on the falling edge of CLK at three quarters of the way
into the bit cell, see Figure 8.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment (i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR). The maximum allowable skew is +4.5 master
clock (CLK) periods forward with resolution of ½ clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70200 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
5
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