LSIs for Gray Scale Font Engine
MN5572
Gray Scale Font Engine
I
Overview
The MN5572 generates shaded gray-scale data from outline (path) data for figures and characters at high speeds. This
IC includes built-in input and output FIFO buffers for high-speed processing, and provides three interface circuits, a
32-bit local bus, a 16-bit local bus, and a PCI bus, so that it can be used in a wide range of application products.
Note) PCI bus is a registered trademark of the (US) Peripheral Component Interconnect Association.
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Features
•
Gray levels: The number of gray levels can be set to any value between 2 and 128.
•
Bit size: The bit size can be set arbitrarily.
•
Generation processing speed: More than 20 000 frames/second (A single frame is 32 dots by 32 dots, when the Heisei
Gothic (Japanese) font is used as the sample data.)
•
Interface specifications: Local bus (16 bits or 32 bits, 33 MHz), PCI bus (32 bits, 33 MHz)
•
Operating frequency: 66 MHz (maximum)
•
Operating supply voltage: 3.3 V
±
0.3 V (5 V inputs are also supported.)
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Applications
•
High-quality character generation in STB, DTV, in-car navigation systems and other products.
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Block Diagrams
•
Local Mode
•
PCI Mode
RAM
MN5572
ROM
Network
MN5572
Graphics
Local Bus
PCI Bus
Bridge
CPU
Host-PCI
Bridge
CPU Bus
CPU
Publication date: November 2001
SDF00008BEM
1
MN5572
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Pin Assignments
1. Pin Assignment in Local 32/16 Mode
ADRS0
VSS
DATA15
DATA14
DATA13
DATA12
VDD
VSS
DATA11
DATA10
DATA9
DATA8
VDD
VSS
DATA7
DATA6
DATA5
DATA4
VDD
VSS
DATA3
DATA2
DATA1
DATA0
N.C.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
ADRS1
ADRS2
ADRS3
NWE
NCS
NRE
VDD
DATA16
DATA17
DATA18
DATA19
VSS
VDD
DATA20
DATA21
DATA22
DATA23
VSS
VDD
DATA24
DATA25
DATA26
DATA27
VSS
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
N.C.
VDD
DATA28
DATA29
DATA30
DATA31
VSS
VDD
WAIT
NDEVSEL
NSTOP
PAR
NPERR
NSERR
VSS
NRST
VDD
HOSTCLK
VSS
P2VSS
P2VDD
P2TCPOUT
P2NPWD
PLTPDIN
PLNRESET
Note) N.C.: No connection.
2
VDD
VSS
IRQ
MINTEST
TESTON
IFCFG
BUSSEL
CLKSEL2
CLKSEL1
CLKSEL0
MIN5
VDD
OCLOCK
VSS
ICLOCK
VDD
CAPTON
P1VDD
P1VSS
P1TCPOUT
P1SEL2
P1SEL1
P1NPWD
PLTEST
N.C.
(TOP VIEW)
SDF00008BEM
MN5572
I
Pin Assignments (continued)
2. Pin Assignment in PCI Mode
NCBE0
VSS
AD15
AD14
AD13
AD12
VDD
VSS
AD11
AD10
AD9
AD8
VDD
VSS
AD7
AD6
AD5
AD4
VDD
VSS
AD3
AD2
AD1
AD0
N.C.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
N.C.
NCBE1
NCBE2
NCBE3
NIRDY
NFRAME
IDSEL
VDD
AD16
AD17
AD18
AD19
VSS
VDD
AD20
AD21
AD22
AD23
VSS
VDD
AD24
AD25
AD26
AD27
VSS
N.C.
VDD
AD28
AD29
AD30
AD31
VSS
VDD
NTRDY
NDEVSEL
NSTOP
PAR
NPERR
NSERR
VSS
NRST
VDD
PCICLK
VSS
P2VSS
P2VDD
P2TCPOUT
P2NPWD
PLTPDIN
PLNRESET
Note) N.C.: No connection.
VDD
VSS
IRQ
MINTEST
TESTON
IFCFG
BUSSEL
CLKSEL2
CLKSEL1
CLKSEL0
MIN5
VDD
OCLOCK
VSS
ICLOCK
VDD
CAPTON
P1VDD
P1VSS
P1TCPOUT
P1SEL2
P1SEL1
P1NPWD
PLTEST
N.C.
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDF00008BEM
3
MN5572
I
Pin Descriptions
1. Local 32 mode pin descriptions
Pin Name
ICLOCK
HOSTCLK
NRST
ADRS[3 : 0]
NCS
NWE
NRE
DATA[31 : 16]
DATA[15 : 0]
WAIT
IRQ
IFCFG
BUSSEL
CLKSEL[2 : 0]
PLNRESET
P1NPWD
P1SEL[2 : 1]
P2NPWD
OCLOCK
NSERR
NPERR
PAR
NSTOP
NDEVSEL
MINTEST
TESTON
CAPTON
PLTEST
PLTPDIN
P1TCPOUT
P2TCPOUT
MIN5
P1VDD
P2VDD
VDD
I/O
I
I
I
I
I
I
I
I/O
I/O
O
O
I
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
O
O
I
I
I
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Internal operating clock input
External interface clock input
Hardware reset (active low)
Address input from host
Chip select from host (active low)
Write enable from host (active low)
Read enable from host (active low)
Data I/O to/from host (upper 16 bits)
Data I/O to/from host (lower 16 bits)
Wait output to host
Interrupt request output to host
Interface mode setting (connect low)
Data bus width setting (connect high)
Internal/external clock setting
Internal PLL reset (active low)
Low power mode control for internal frequency multiplier PLL (active low)
Frequency selector for internal frequency multiplier PLL
Low power mode control for external phase compensation PLL (active low)
Unused
Unused
Unused
Unused
Unused
Unused
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing
Testing
5 V voltage reference
Internal frequency multiplier PLL power supply (3.3 V)
External phase compensation PLL power supply (3.3 V)
Power supply (3.3 V)
Description
4
SDF00008BEM
MN5572
I
Pin Descriptions (continued)
1. Local 32 mode pin descriptions (continued)
Pin Name
P1VSS
P2VSS
VSS
I/O
Ground
Ground
Ground
Description
2. Local 16 mode pin descriptions
Pin Name
ICLOCK
HOSTCLK
NRST
ADRS[3 : 0]
NCS
NWE
NRE
DATA[31 : 16]
DATA[15 : 0]
WAIT
IRQ
IFCFG
BUSSEL
CLKSEL[2 : 0]
PLNRESET
P1NPWD
P1SEL[2 : 1]
P2NPWD
OCLOCK
NSERR
NPERR
PAR
NSTOP
NDEVSEL
MINTEST
TESTON
CAPTON
PLTEST
PLTPDIN
I/O
I
I
I
I
I
I
I
I
I/O
O
O
I
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
Internal operating clock input
External interface clock input
Hardware reset (active low)
Address input from host
Chip select from host (active low)
Write enable from host (active low)
Read enable from host (active low)
Unused
Data I/O to/from host (upper 16 bits)
Wait output to host
Interrupt request output to host
Interface mode setting (connect low)
Data bus width setting (connect low)
Internal/external clock setting
Internal PLL reset (active low)
Low power mode control for internal frequency multiplier PLL (active low)
Frequency selector for internal frequency multiplier PLL
Low power mode control for external phase compensation PLL (active low)
Unused
Unused
Unused
Unused
Unused
Unused
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Testing (Connect low during normal operation.)
Description
SDF00008BEM
5
嵌入式系统
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