CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9 and 4,096 x 9
Integrated Device Technology, Inc.
IDT72132
IDT72142
FEATURES:
• 35ns parallel-port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 8, 9, 16-18, and
32-36 bit using Flexshift™ serial input without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CMOS
technology
• Available in the 28-pin plastic DIP
• Industrial temperature range (–40
o
C to +85
o
C)
DESCRIPTION:
The IDT72132/72142 are high-speed, low-power serial-to-
parallel FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). These devices can be configured with
the IDTs parallel-to-serial FIFOs (IDT72131/72141) for bidi-
rectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
built using multiple IDT72132/72142 chips. IDTs unique
Flexshift serial expansion logic (SIX,
NW
) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. These devices can also be directly connected for
depth expansion.
Five flags are provided to monitor the FIFO. The Full and
Empty flags prevent any FIFO data overflow or underflow
conditions. The Almost-Full (7/8), Half-Full, and Almost-Empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72132/72142 is fabricated using IDTs high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
SICP
SIX
SI
D
7
D
8
PIN CONFIGURATION
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D
7
D
8
/
SERIAL INPUT
CIRCUITRY
FLAG
LOGIC
GND
2
3
4
5
NEXT WRITE
POINTER
RAM ARRAY
2,048 x 9
4,096 x 9
READ
POINTER
Q
0
Q
1
Q
2
Q
3
Q
4
GND
Q
5
6
7
8
9
10
11
12
13
14
SI
SICP
SIX
/
RESET
LOGIC
/
GND
Q
8
Q
7
EXPANSION
LOGIC
Q
0
-Q
8
2752 drw 01
Q
6
2752 drw 02
PLASTIC DIP (P28-1, order code: P)
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1999
DSC-2752/-
1
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
SI
Name
Serial Input
Reset
I/O
I
I
Description
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus D
7
, D
8
determine which device stores the data.
When
RS
is set LOW, internal READ and WRITE pointers are set to the first location of the
RAM array.
HF
and
FF
go HIGH, and
AEF
, and
EF
go LOW. A reset is required before an initial
WRITE after power-up.
R
must be HIGH during an
RS
cycle.
To program the Serial In word width , connect
NW
with one of the Data Set pins (D
7
, D
8
).
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
When READ is LOW, data can be read from the RAM array sequentially, independent of SICP.
In order for READ to be active,
EF
must be HIGH. When the FIFO is empty (
EF
-LOW), the
internal READ operation is blocked and Q
0
-Q
8
are in a high impedance condition.
This is a dual-purpose input. In the single device configuration (
XI
grounded), activating
retransmit (
FL
/
RT
-LOW) will set the internal READ pointer to the first location. There is no
effect on the WRITE pointer.
R
must be HIGH and SICP must be LOW before setting
FL
/
RT
LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,
FL
/
RT
grounded indicates the first activated device.
In the single device configuration,
XI
is grounded. In depth expansion or daisy chain
expansion,
XI
is connected to
XO
(expansion out) of the previous device.
RS
NW
SICP
Next Write
Serial Input Clock
Read
I
I
I
R
FL
/
RT
First Load/
Retransmit
I
XI
SIX
Expansion In
Serial Input
Expansion
I
I
In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin
of all other devices is connected to the D
7
or D
8
pin of the previous device. For single device
operation, SIX is tied HIGH.
When
OE
is set LOW, the parallel output buffers receive data from the RAM array. When
OE
is set HIGH, parallel three state buffers inhibit data flow.
Data outputs for 9-bit wide data.
When
FF
goes LOW, the device is full and data must not be clocked by SICP. When
HIGH, the device is not full. See the diagram on page 7 for more details.
OE
Q
0
–Q
8
Output Enable
Output Data
Full Flag
Empty Flag
Almost-Empty/
Almost-Full Flag
Expansion Out/
Half-Full Flag
I
O
O
O
O
O
FF
EF
AEF
XO
/
HF
FF
is
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH, the device is not empty.
When
AEF
is LOW, the device is empty to 1/8 full or 7/8 to completely full. When
AEF
is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
This is a dual-purpose output. In the single device configuration (
XI
grounded), the device is
more than half full when
HF
is LOW. In the depth expansion configuration (
XO
connected to
XI
of the next device), a pulse is sent from
XO
to
XI
when the last location in the RAM array
is filled.
D
7
, D
8
Data Set
O
The appropriate Data Set pin (D
7
, D
8
) is connected to
NW
to program the Serial In data word
width. For example: D
7
-
NW
programs a 8-bit word width, D
8
-
NW
programs a 9-bit word
width, etc.
Single Power Supply of 5V.
Three grounds at 0V.
2752 tbl 01
V
CC
GND
Power Supply
Ground
STATUS FLAGS
Number of Words in FIFO
IDT72132
0
1-255
256-1,024
1,025-1,792
1,793-2,047
2,048
IDT72142
0
1-511
512-2,048
2,049-3,584
3,585-4,095
4,096
FF
H
H
H
H
H
L
AEF
L
L
H
H
L
L
HF
H
H
H
L
L
L
EF
L
H
H
H
H
H
2752 tbl 02
2
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
–55 to +125
–50 to +50
°C
mA
Commercial
–0.5 to +7.0
Unit
V
RECOMMENDED DC OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL(1)
T
A
Parameter
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input Low Voltage
Min.
4.5
0
2.0
—
Typ.
5.0
0
—
—
—
Max. Unit
5.5
0
—
0.8
+85
V
V
V
V
°C
2752 tbl 04
NOTE:
2752 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Operating Temperature -40
Industrial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
2752 tbl 05
NOTE:
1. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V
±
10%, T
A
= -40°C to +85°C)
IDT72132
IDT72142
Industrial
Symbol
I
IL
(1)
I
OL
(2)
V
OH
V
OL
I
CC1
(3)
I
CC2
(3,4)
I
CC3
(3,4)
Parameter
Input Leakage Current
(Any Input)
Output Leakage Current
Output Logic "1" Voltage,
I
OUT
= –2mA
Output Logic "0" Voltage,
I
OUT
= 8mA
Active Power Supply Current
Standby Current
(
R
=
RS
=
FL
/
RT
= V
IH
; SICP = V
IL
)
Power Down Current
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
90
8
—
Max.
1
10
—
0.4
140
12
2
Unit
µA
µA
V
V
mA
mA
mA
2752 tbl 06
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2. R
≤
V
IL
, 0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open (I
OUT
= 0).
4.
RS
=
FL
/
RT
=
R
= V
CC
-0.2V; SICP
≤
0.2V; all other inputs = V
CC
- 0.2V or GND + 0.2V, which toggle at 20 MHz.
3
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V
±
10%, T
A
= -40°C to +85°C)
Industrial
IDT72132L35
IDT72132L50
IDT72142L35
IDT72142L50
Min.
Max.
Min.
Max.
—
22.2
—
15
—
50
—
40
—
10
35
45
5
—
5
—
5
—
12
0
5
8
—
—
—
15
—
—
—
35
45
35
35
10
—
—
20
5
45
35
35
10
—
—
35
10
16
35
—
—
—
—
20
—
15
—
20
—
—
—
—
45
30
45
—
30
30
45
—
—
—
—
—
45
45
—
17
—
—
—
—
40
40
—
—
—
—
15
50
65
10
—
5
—
5
—
15
0
5
10
—
—
—
15
—
—
—
50
65
50
50
15
—
—
35
5
65
50
50
15
—
—
50
10
15
50
—
—
—
—
30
—
15
—
22
—
—
—
—
65
40
65
—
45
45
65
—
—
—
—
—
65
65
—
20
—
—
—
—
50
50
—
—
—
Symbol
Parameter
t
S
Parallel Shift Frequency
t
SICP
Serial-InShift Frequency
PARALLEL OUTPUT TIMINGS
t
A
Access Time
t
RR
Read Recovery Time
t
RPW
Read Pulse Width
t
RC
Read Cycle Time
t
RLZ
Read Pulse LOW to Data Bus at Low-Z
(1)
t
RHZ
Read Pulse HIGH to Data Bus at High-Z
(1)
t
DV
Data Valid from Read Pulse HIGH
t
OEHZ
Output Enable to High-Z (Disable)
(1)
t
OELZ
Output Enable to Low-Z (Enable)
(1)
t
AOE
Output Enable to Data Valid (Q
0-8
)
SERIAL INPUT TIMINGS
t
SIS
Serial Data in Set-Up Time to SICP Rising Edge
t
SIH
Serial Data in Hold Time to SICP Rising Edge
t
SIX
SIX Set-Up Time to SICP Rising Edge
t
SICW
Serial-In Clock Width HIGH/LOW
FLAG TIMINGS
t
SICEF
SICP Rising Edge (Last Bit - First Word) to
EF
HIGH
t
SICFF
SICP Rising Edge (Bit 1 - Last Word) to
FF
LOW
t
SICF
SICP Rising Edge to
HF
,
AEF
t
RFFSI
Recovery Time SICP After
FF
Goes HIGH
t
REF
Read LOW to
EF
LOW
t
RFF
Read HIGH to
FF
HIGH
t
RF
Read HIGH to Transitioning
HF
and
AEF
t
RPE
Read Pulse Width After
EF
HIGH
RESET TIMINGS
t
RSC
Reset Cycle Time
t
RS
Reset Pulse Width
t
RSS
Reset Set-up Time
t
RSR
Reset Recovery Time
t
RSF1
Reset to
EF
and
AEF
LOW
t
RSF2
Reset to
HF
and
FF
HIGH
t
RSDL
Reset to D LOW
t
POI
SICP Rising Edge to D
RETRANSMIT TIMINGS
t
RTC
Retransmit Cycle Time
t
RT
Retransmit Pulse Width
t
RTS
Retransmit Set-up Time
t
RTR
Retransmit Recovery Time
DEPTH EXPANSION MODE TIMINGS
t
XOL
Read/Write to
XO
LOW
t
XOH
Read/Write to
XO
HIGH
t
XI
XI
Pulse Width
t
XIR
XI
Recovery Time
t
XIS
XI
Set-up Time
NOTE:
1. Guaranteed by design minimum times, not tested
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2752 tbl 07
4
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
2752 tbl 08
5V
1.1KΩ
D.U.T.
680Ω
30pF*
2752 drw 03
or equivalent circuit
Figure A. Output Load
*Includies jig and scope capacitances
FUNCTIONAL DESCRIPTION
Serial Data Input
The serial data is input on the SI pin. The data is clocked
in on the rising edge of SICP providing the Full Flag (
FF
) is not
asserted. If the Full Flag is asserted then the next parallel data
word is inhibited from moving into the RAM array. NOTE:
SICP should not be clocked once the last bit of the last word
has been shifted in, as indicated by
NW
HIGH and
FF
LOW.
If it is, then the input data will be lost.
The serial word is shifted in Least Significant Bit first. Thus,
when the FIFO is read, the Least Significant Bit will come out
on Q
0
and the second bit is on Q
1
and so on. The serial word
width must be programmed by connecting the appropriate
Data Set line (D
7
, D
8
) to the
NW
input. The data set lines are
taps off a digital delay line. Selecting one of these taps
programs the width of the serial word to be written in.
Parallel Data Output
A read cycle is initiated on the falling edge of Read (
R
)
provided the Empty Flag is not set. The output data is
accessed on a first-in/first-out basis, independent of the
ongoing write operations. The data is available t
A
after the
falling edge of
R
and the output bus Q goes into high imped-
ance after
R
goes HIGH.
Alternately, the user can access the FIFO by keeping
R
LOW and enabling data on the bus by asserting Output
Enable (
OE
). When
R
is LOW, the
OE
signal enables data on
the output bus. When
R
is LOW and
OE
is HIGH, the output
bus is three-stated. When
R
is HIGH, the output bus is
disabled irrespective of
OE
.
t
RSC
t
RS
t
RSS
SICP
t
RSS
t
RSR
0
n-1
(1)
t
RSF1
,
t
RSF2
,
t
RSDL
D
7
,D
8
2752 drw 04
t
PDI
NOTE:
1. Input bits are numbered 0 to n-1. D
7
and D
8
correspond to n=8 and n=9 respectively
Figure 1. Reset
5
PCB设计
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