DATASHEET
ISL6615A
High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features
The ISL6615A is a high-speed MOSFET driver optimized to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. This driver,
combined with an Intersil Digital or Analog multiphase PWM
controller, forms a complete high frequency and high
efficiency voltage regulator.
The ISL6615A drives both upper and lower gates over a range
of 4.5V to 13.2V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses.
The ISL6615A features 6A typical sink current for the low-side
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to the
high dV/dt of the switching node.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize the dead-time.
The ISL6615A includes an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at which
the PHASE node is connected to the gate of the low side
MOSFET (LGATE). The output voltage of the converter is then
limited by the threshold of the low side MOSFET, which
provides some protection to the load if the upper MOSFET(s) is
shorted.
The ISL6615A also features an input that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevent negative transients on
the controlled output voltage when operation is suspended.
This feature eliminates the need for the Schottky diode that
may be utilized in a power system to protect the load from
negative output voltage damage.
FN6608
Rev 2.00
April 13, 2012
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- LGATE Detection
- Auto-zero of r
DS(ON)
Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 6A LGATE Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Support 5V PWM Input Logic
• Tri-State PWM Input for Safe Output Stage Shutdown
• Tri-State PWM Input Hysteresis for Applications with Power
Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper PAD for Better Heat Spreading
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-free (RoHS compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current Low-Profile DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• Synchronous Rectification for Isolated Power Supplies
Related Literature
• Technical Brief
TB363
“Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief
TB389
“PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
FN6608 Rev 2.00
April 13, 2012
Page 1 of 13
ISL6615A
Block Diagram
(UVCC)
VCC
+5V
10k
PWM
POR/
CONTROL
8k
LOGIC
PRE-POR OVP
FEATURES
ISL6615A
BOOT
UGATE
PHASE
(LVCC)
PVCC
SHOOT-
THROUGH
PROTECTION
UVCC = PVCC
LGATE
GND
SUBSTRATE RESISTANCE
PAD
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
Typical Application - 2 Channel Converter
V
IN
+7V TO +13.2V
+5V
+5V
PVCC
VCC
PWM1
PWM2
PWM
CONTROL
(ISL63xx
OR ISL65xx)
VID
(OPTIONAL)
ISEN1
ISEN2
+7V TO +13.2V
V
IN
PWM
ISL6615A
PHASE
LGATE
BOOT
UGATE
FB
VCC
VSEN
COMP
PGOOD
GND
+V
CORE
PVCC
FS/EN
GND
VCC
PWM
BOOT
UGATE
ISL6615A
PHASE
LGATE
GND
THE ISL6615A CAN SUPPORT 5V PWM INPUT
FN6608 Rev 2.00
April 13, 2012
Page 2 of 13
ISL6615A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6615ACBZ
ISL6615ACRZ
ISL6615AIBZ
ISL6615AIRZ
ISL6615AFRZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL6615A.
For more information on MSL please see techbrief
TB363.
615A
6615A IBZ
15AI
15AF
PART
MARKING
6615A CBZ
TEMP.
RANGE (°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +125
8 Ld SOIC
10 Ld 3x3 DFN
8 Ld SOIC
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PACKAGE
(Pb-free)
PKG.
DWG. #
M8.15
L10.3x3
M8.15
L10.3x3
L10.3x3
Pin Configurations
ISL6615A
(8 LD SOIC)
TOP VIEW
8
7
6
5
PHASE
PVCC
VCC
LGATE
UGATE
BOOT
N/C
PWM
GND
1
2
3
4
5
ISL6615A
(10 LD 3x3 DFN)
TOP VIEW
10 PHASE
9 PVCC
GND
8 N/C
7 VCC
6 LGATE
UGATE
BOOT
PWM
GND
1
2
3
4
*RECOMMEND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC
Functional Pin Descriptions
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device “TIMING DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the
“TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of the
controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high quality
low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return
path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
-
3
3, 8
4
N/C
PWM
4
5
6
7
8
9
5
6
7
9
10
11
GND
LGATE
VCC
PVCC
PHASE
PAD
FN6608 Rev 2.00
April 13, 2012
Page 3 of 13
ISL6615A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
. . . . . . . . . . . .VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
. . . . . . . . . . . . . . . . .GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V (<200ns, VBOOT-GND < 36V))
ESD Ratings
HBM (Tested per JESD22-A114E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
MM (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
CDM (Tested per JESD22-C101C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Latchup . . . . . . . . . . . . . . . . . . . . . . Tested per JESD78A, Class II at +85°C
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
SOIC Package (Notes 4, 5) . . . . . . . . . . . . . 98
56
DFN Package (Notes 6, 7) . . . . . . . . . . . . . 47
5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6615ACRZ, ISL6615ACBZ . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6615AIRZ, ISL6615AIBZ . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ISL6615AFRZ (Note 8). . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . .+125°C
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air.
5. For
JC
, the “case temp” location is taken at the package top center.
6.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. When using ISL6615AFRZ, care should be taken to minimize power dissipation.
Electrical Specifications
PARAMETER
Recommended Operating Conditions; Boldface limits apply over the operating temperature ranges.
SYMBOL
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
I
VCC
I
PVCC
f
PWM
= 300kHz, V
VCC
= 12V
f
PWM
= 300kHz, V
PVCC
= 12V
-
-
4.5
8
-
-
mA
mA
POWER-ON RESET AND ENABLE
VCC Rising Threshold
VCC Falling Threshold
6.1
4.7
6.4
5.0
6.7
5.3
V
V
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current
I
PWM
V
PWM
= 5V
V
PWM
= 0V
PWM Rising Threshold (Note 10)
PWM Falling Threshold (Note 10)
Typical Tri-State Shutdown Window
Tri-State Lower Gate Falling Threshold
Tri-State Lower Gate Rising Threshold
Tri-State Upper Gate Rising Threshold
Tri-State Upper Gate Falling Threshold
Shutdown Holdoff Time
UGATE Rise Time (Note 10)
LGATE Rise Time (Note 10)
t
TSSHD
t
RU
t
RL
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 10% to 90%
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
-
-
1.80
-
-
-
-
-
-
-
510
-475
3.00
2.00
-
1.50
1.00
3.20
2.70
55
13
10
-
-
-
-
2.40
-
-
-
-
-
-
-
µA
µA
V
V
V
V
V
V
V
ns
ns
ns
FN6608 Rev 2.00
April 13, 2012
Page 4 of 13
ISL6615A
Electrical Specifications
PARAMETER
UGATE Fall Time (Note 10)
LGATE Fall Time (Note 10)
UGATE Turn-On Propagation Delay
(Note 10)
LGATE Turn-On Propagation Delay
(Note 10)
UGATE Turn-Off Propagation Delay
(Note 10)
LGATE Turn-Off Propagation Delay
(Note 10)
LG/UG Tri-State Propagation Delay
(Note 10)
Recommended Operating Conditions; Boldface limits apply over the operating temperature ranges. (Continued)
SYMBOL
t
FU
t
FL
t
PDHU
t
PDHL
t
PDLU
t
PDLL
t
PDTS
TEST CONDITIONS
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
MIN
(Note 9)
-
-
-
-
-
-
-
TYP
10
10
30
20
10
20
20
MAX
(Note 9)
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
OUTPUT (Note 10)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Limits established by characterization and are not production tested.
I
U_SOURCE
R
U_SOURCE
I
U_SINK
R
U_SINK
I
L_SOURCE
R
L_SOURCE
I
L_SINK
R
L_SINK
V
PVCC
= 12V, 3nF Load
150mA Source Current
V
PVCC
= 12V, 3nF Load
150mA Sink Current
V
PVCC
= 12V, 3nF Load
150mA Source Current
V
PVCC
= 12V, 3nF Load
150mA Sink Current
-
-
-
-
-
-
-
-
2.5
1
4
0.8
4
0.7
6
0.45
-
-
-
-
-
-
-
-
A
A
A
A
FN6608 Rev 2.00
April 13, 2012
Page 5 of 13
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