MAX12_C ...........................................................0°C to +70°C
MAX12_E_ .................................................... -40°C to +85°C
MAX12_MRG .............................................. -55°C to +125°C
Storage Temperature Range ..............................-65°C to+160°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
PARAMETER
ACCURACY
Resolution
(V
DD
= +4.75V to +5.25V, V
SS
= -10.8V to -15.75V, f
CLK
= 8MHz for MAX120 and 5MHz for MAX122, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.)
SYMBOL
RES
12-bit no missing
codes over
temperature range
11-bit no missing
codes over
temperature range
MAX122AC/AE
MAX120C/E,
MAX122BC/BE
MAX120M
MAX122AC/AE
INL
MAX120C/E,
MAX122BC/BE
Code 00..00 to 00..01 transition,
near V
AIN
= 0V
Temperature drift
Full-Scale Error (Notes 1, 2)
Full-Scale Temperature Drift
Power-Supply Rejection Ratio
(Change in FS)
(Note 3)
ANALOG INPUT
Input Range
Input Current
Input Capacitance (Note 4)
Full-Power Input Bandwidth
REFERENCE
Output Voltage
External Load Regulation
Temperature Drift (Note 5)
No external load, V
AIN
= 5V, T
A
= +25°C
0mA < I
SINK
< 5mA, V
AIN
= 0V
MAX12_C/E
-5 02
-4.98
5
±25
V
mV
ppm/°C
1.5
V
AIN
= +5V (approximately 6kΩ to REF)
-5
+5
2.5
10
V
mA
pF
MHz
PSRR
Including reference; adjusted for bipolar
zero error; T
A
= +25°C
Excluding reference
V
DD
only, 5V ±5%
V
SS
only, -12V ±10%
V
SS
only, -15V ±5%
±1
±1/4
±1/4
±1/4
±3/4
±1
±1
LSB
±0.005
±8
CONDITIONS
MIN
12
±3/4
±1
LSB
±2
±3/4
±1
±3
LSB
TYP
MAX
UNITS
Bits
Differential Nonlinearity (Note 1)
DNL
Integral Nonlinearity
(Note 1)
Bipolar Zero Error (Note 1)
LSB
LSB/”C
LSB
ppm/”C
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Maxim Integrated
│
2
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Electrical Characteristics (continued)
(V
DD
= +4.75V to +5.25V, V
SS
= -10.8V to -15.75V, f
CLK
= 8MHz for MAX120 and 5MHz for MAX122, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MAX120, MAX122
Signal-to-Noise Plus Distortion
SINAD
T
A
= +25°C
MAX122AC/AE
MAX122BC/BE
T
A
= +25°C
THD
MAX120
MAX122
MAX122AC/AE
MAX122BC/BE
T
A
= +25°C
Spurious-Free Dynamic Range
SFDR
MAX120
MAX122
MAX122AC/AE
MAX122BC/BE
CONVERSION TIME
Synchronous
Clock Frequency
t
CONV
f
CLK
13t
CLK
MAX120
MAX122
MAX120
MAX122
0.1
0.1
2.4
0.8
10
V
IN
= 0V or V
DD
V
OL
V
OH
I
LKG
I
SINK
= 1.6mA
I
SOURCE
= 1mA
V
IN
= 0V or V
DD
, D11–D0
V
DD
- 0.5
±5
10
V
DD
V
SS
I
DD
I
SS
Guaranteed by supply rejection test
Guaranteed by supply rejection test
V
DD
= 5.25V, V
SS
= -15.75V, V
AIN
= 0V
V
DD
= 5.25V, V
SS
= -15.75V, V
AIN
= 0V
V
DD
= 5V, V
SS
= -12V, V
AIN
= 0V
4.75
-10.80
9
14
210
5.25
-15.75
15
20
315
±5
0.4
1.63
2.60
8
5
µs
MHz
77
78
77
75
82
85
dB
MIN
70
70
69
-82
-85
-77
-78
-77
-75
dB
TYP
72
dB
MAX
UNITS
DYNAMIC PERFORMANCE (MAX120: f
S
= 500kHz, V
AIN
= ±5V
P-P
, 100kHz: MAX122: f
S
= 333kHz, V
AIN
= ±5V
P-P
, 50kHz
Total Harmonic Distortion
(First Five Harmonics)
DIGITAL INPUTS (CLKIN,
CONVST, RD, CS)
Input High Voltage
Input Low Voltage
Input Capacitance (Note 4)
Input Current
DIGITAL OUTPUTS (INT/BUSY, D11–D0)
Output Low Voltage
Output High Voltage
Leakage Current
Output Capacitance (Note 4)
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current (Note 6)
Negative Supply Current (Note 6)
Power Dissipation (Note 6)
V
V
mA
mA
mW
V
V
µA
pF
V
IH
V
IL
V
V
pF
µA
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Maxim Integrated
│
3
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Timing Characteristics
(V
DD
= +5V, V
SS
= -12V to -15V, 100% tested, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 7)
PARAMETER
CS
to
RD
Setup Time
CS
to
RD
Hold Time
CONVST
Pulse Width
RD
Pulse Width
Data-Access Time
Bus-Relinquish Time
RD
or
CONVST
to
BUSY
CLKIN to
BUSY
or
INT
CLKIN to
BUSY
Low
RD
to
INT
High
BUSY
or
INT
to Data Valid
Acquisition Time (Note 8)
Aperture Delay (Note 8)
Aperture Jitter (Note 8)
SYMBOL
t
CS
t
CH
t
CW
t
RW
t
DA
t
DH
t
B0
t
B1
t
B2
t
IH
t
BD
t
ACQ
t
AP
C
L
= 50pF
C
L
= 50pF
In mode 5
C
L
= 50pF
C
L
(Data) = 100pF,
C
L
(INT,
BUSY)
= 50pF
350
10
30
C
L
= 100pF
CONDITIONS
T
A
= +25°C
MIN
0
0
30
t
DA
40
30
30
70
45
30
75
50
75
110
90
50
20
350
TYP
MAX
MIN
0
0
30
t
DA
100
65
100
150
120
75
30
MAX12_C/E
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
Note 1:
These tests are performed at V
DD
= 5V, V
SS
= -15V. Operation over supply is guaranteed by supply rejection tests.
Note 2:
Ideal full-scale transition is at +5V - 3/2 LSB = +4.9963V, adjusted for offset error.
Note 3:
Supply rejection defined as change in full-scale transition voltage with the specified change in supply voltage = (FS at nomi-
nal supply)- (FS at nominal supply ± tolerance), expressed in LSBs.
Note 4:
For design guidance only, not tested.
Note 5:
Temperature drift is defined as the change in output voltage from +25°C to T
MIN
or T
MAX
. It is calculated as T
C
= ΔV
REF
/
V
REF
/(ΔT).
Note 6:
V
CS
= V
RD
= V
CONVST
= 0V, V
MODE
= 5V.
Note 7:
Control inputs specified with t
r
= t
f
= 5ns ( 10% to 90% of +5V) and timed from a 1.6V voltage level. Output delays are
measured to +0.8V if going low, or +2.4V if going high. For bus-relinquish time, a change of 0.5V is measured. See Figures
1 and 2 for load circuits.
Note 8:
For design guidance only, not tested.
Pin Description
PIN
NAME
FUNCTION
Mode Input. Hardwire to set operational mode.
V
DD
: Single conversion,
INT
Output
OPEN: Single conversion,
BUSY
Output
DGND: Continuous conversions,
BUSY
Output
Negative Power Supply, -12V or -15V
Positive Power Supply, +5V
Sampling Analog Input, ±5V bipolar input range
-5V Reference Output. Bypass to AGND with 22µF || 0.1µF.
1
MODE
2
3
4
5
V
SS
V
DD
AIN
V
REF
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Maxim Integrated
│
4
MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Pin Description (continued)
PIN
6
7–11, 13–19
12
20
21
22
23
24
NAME
AGND
D11–D0
DGND
CONVST
CLKIN
INT/BUSY
CS
RD
Analog Ground
Three-State Data Outputs D11 (MSB) to D0 (LSB)
Digital Ground
Convert Start Input. Initiates conversions on its falling edge.
Clock Input. Drive with TTL-compatible clock from 0.1MHz to 8MHz (MAX120), 0.1MHz to 5MHz
(MAX122)
Interrupt or Busy Output. Indicates converter status. If MODE is connected to V
DD
, configure
for an
INT
output. If MODE is open or connected to DGND, configure for a
BUSY
output. See
operational diagrams.
Chip-Select Input, Active-Low. When
RD
is low, enables the three-state outputs. If
CONVST
and
RD
are low, a conversion is initiated on the falling edge of
CS.
Read Input, Active-Low. When
CS
is low,
RD
enables the three-state outputs. If
CONVST
and
CS
are low, conversion is initiated on the falling egde of
RD.
FUNCTION
Detailed Description
ADC Operation
The MAX120/MAX122 use successive approximation and
input T/H circuitry to convert an analog signal to a series
of 12-bit digital-output codes. The control logic interfaces
easily to most µPs, requiring only a few passive compo-
nents tor most applications. The T/H does not require an
external capacitor. Figure 3 shows the MAX120/MAX122
in the simplest operational configuration.
Analog Input Track/Hold
Figure 4 shows the equivalent input circuit, illustrating the
sampling architecture of the ADC’s analog comparator.
An internal buffer charges the hold capacitor to minimize
the required acquisition time between conversions. The
analog input appears as a 6kΩ resistor in parallel with a
10pF capacitor.
Between conversions, the buffer input is connected to AIN
through the input resistance. When a conversion starts,
the buffer input disconnects from AIN, thus sampling the
input. At the end of the conversion, the buffer input recon-
nects to AIN, and the hold capacitor once again charges
to the input voltage.
The T/H is in tracking mode whenever a conversion is
NOT in progress. Hold mode starts approximately 10ns
after a conversion is initiated. Variation in this delay from
one conversion to the next (aperture jitter) is typically
30ps. Figures 7 through 11 detail the T/H mode and inter-
我的程序中有7组双向端口，1组8位，用到了7个高阻态，这时quartusII就提示
Error: Design requires 7 output enable signals, but the device can contain only 6 output enable signals
我用 ......
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