NCP1571
Low Voltage Synchronous
Buck Controller
The NCP1571 is a low voltage buck controller. It provides the
control for a DC−DC power solution producing an output voltage as
low as 0.980 V over a wide current range. The NCP1571−based
solution is powered from 12 V with the output derived from a 2−7 V
supply. It contains all required circuitry for a synchronous NFET buck
regulator using the V
2
t
control method to achieve the fastest possible
transient response and best overall regulation. NCP1571 operates at a
fixed internal 200 kHz frequency and is packaged in an SOIC−8.
This device provides undervoltage lockout protection, Soft−Start,
Power Good with delay, and built−in adaptive non−overlap. During
undervoltage lockout, the NCP1571 controller allows the power
supply output to drift down, allowing the load time to shut off. This
operation distinguishes the NCP1571 from other parts in its family.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
1571
ALYW
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Pb−Free Package is Available
0.980 V
±
1.0% Reference Voltage
V
2
Control Topology
200 ns Transient Response
Programmable Soft−Start
Power Good
Programmable Power Good Delay
40 ns Gate Rise and Fall Times (3.3 nF Load)
Adaptive FET Non−Overlap Time
Fixed 200 kHz Oscillator Frequency
Undervoltage Lockout Holds Both Gate Outputs Low
On/Off Control Through Use of the COMP Pin
Overvoltage Protection through Synchronous MOSFETs
Synchronous N−Channel Buck Design
Dual Supply, 12 V Control, 2−7 V Power Source
PIN CONNECTIONS
V
CC
PWRGD
PGDELAY
COMP
1
8
GND
V
FB
GATE(L)
GATE(H)
ORDERING INFORMATION
Device
NCP1571D
NCP1571DR2
NCP1571DR2G
Package
SOIC−8
SOIC−8
SOIC−8
(Pb−Free)
Shipping
†
98 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2004
1
October, 2004 − Rev. 4
Publication Order Number
NCP1571/D
NCP1571
12 V PWRGD V
LOGIC
R1
50 k
C4
0.47
mF
R4
10
PWRGD
NCP1571
PGDELAY
COMP
C13
0.1
mF
V
FB
V
CC
GND
100 pF
C6
NTD4302
Q1
2.7
mH
L1
+
+
+
+
GND
5.0 V
33
mF/8.0
V/1.6 Arms
C1
+
+
C2
+
C3
2.5 V/10 A
GATE(L)
GATE(H)
NTD4302
Q2
5.1 k
R3
C8
C9
C10
C11
GND
C12
0.01
mF
R5
3.3 k
56
mF/4.0
V/1.6 Arms
SP−CAP 40 mW
Figure 1. Applications Circuit
MAXIMUM RATINGS
Rating
Operating Junction Temperature
Storage Temperature Range
ESD Susceptibility (Human Body Model)
Lead Temperature Soldering:
Moisture Sensitivity Level
Package Thermal Resistance, SOIC−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
Reflow: (Note 1)
Value
150
−65 to 150
2.0
230 peak
2
48
165
Unit
°C
°C
kV
°C
−
°C/W
°C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name
IC Power Input
Compensation Capacitor
Voltage Feedback Input
Power Good Output
Power Good Delay
High−Side FET Driver
Low−Side FET Driver
Ground
Pin Symbol
V
CC
COMP
V
FB
PWRGD
PGDELAY
GATE(H)
GATE(L)
GND
V
MAX
15 V
6.0 V
6.0 V
15 V
6.0 V
15 V
15 V
0.5 V
V
MIN
−0.5 V
−0.5 V
−0.5 V
−0.5 V
−0.5 V
−0.5 V
−2.0 V for 50 ns
−0.5 V
−2.0 V for 50 ns
−0.5 V
I
SOURCE
N/A
10 mA
1.0 mA
1.0 mA
1.0 mA
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
1.5 A Peak
450 mA DC
I
SINK
1.5 A Peak
450 mA DC
10 mA
1.0 mA
20 mA
10 mA
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
N/A
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NCP1571
ELECTRICAL CHARACTERISTICS
(0°C < T
J
< 125°C, 11.4 V < V
CC
< 12.6 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
C
PGDELAY
= 0.01
mF,
C
COMP
= 0.1
mF;
unless otherwise specified.)
Characteristic
Error Amplifier
V
FB
Bias Current
COMP Source Current
COMP Sink Current
Reference Voltage
COMP Max Voltage
COMP Min Voltage
COMP Fault Discharge Current at UVLO
COMP Fault Discharge Threshold to
Reset UVLO
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
Output Transconductance
Output Impedance
GATE(H) and GATE(L)
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
Minimum Pulse Width
High Voltage (AC)
1.0 V < GATE(L), GATE(H) < V
CC
− 2.0 V
V
CC
− 2.0 V < GATE(L), GATE(H) < 1.0 V
GATE(H) < 2.0 V, GATE(L) > 2.0 V
GATE(L) < 2.0 V, GATE(H) > 2.0 V
GATE(X) = 4.0 V
Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
Note 2
Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
Note 2
Resistance to GND. Note 2
−
−
40
40
−
V
CC
− 0.5
40
40
60
60
250
V
CC
80
80
100
100
−
−
ns
ns
ns
ns
ns
V
V
FB
= 0 V
COMP = 1.5 V, V
FB
= 0.8 V
COMP = 1.5 V, V
FB
= 1.2 V
COMP = V
FB
T
J
< 25°C
V
FB
= 0.8 V
V
FB
= 1.2 V
COMP = 1.2 V, V
CC
= 6.9 V
−
−
−
−
−
−
−
15
15
0.970
0.965
2.4
−
0.5
0.1
−
−
−
−
−
0.2
30
30
0.980
0.980
2.7
0.1
1.7
0.25
98
20
70
32
2.5
2.0
60
60
0.990
0.995
−
0.2
−
0.3
−
−
−
−
−
mA
mA
mA
V
V
V
V
mA
V
dB
kHz
dB
mmho
MW
Test Conditions
Min
Typ
Max
Unit
Low Voltage (AC)
−
0
0.5
V
GATE(H)/(L) Pulldown
Power Good
Lower Threshold, V
O
Rising
20
50
115
kW
T
J
< 25°C
Lower Threshold, V
O
Falling
T
J
< 25°C
PWRGD Low Voltage
Delay Charge Current
Delay Clamp Voltage
Delay Charge Threshold
Delay Discharge Current at UVLO
I
SINK
= 1.0 mA, V
FB
= 0 V
PGDELAY = 2.0 V
−
Ramp PGDELAY, Monitor PWRGD
PGDELAY = 0.5 V, V
CC
= 6.9 V
0.852
0.847
0.663
0.658
−
7.0
3.45
3.1
0.5
0.882
0.882
0.685
0.685
0.15
12
4.0
3.3
2.0
0.912
0.917
0.709
0.714
0.4
18
4.3
3.5
−
V
V
V
V
V
mA
V
V
mA
2. Guaranteed by design. Not tested in production.
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NCP1571
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
J
< 125°C, 11.4 V < V
CC
< 12.6 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
C
PGDELAY
= 0.01
mF,
C
COMP
= 0.1
mF;
unless otherwise specified.)
Characteristic
Power Good
Delay Discharge Threshold to Reset UVLO
PGDELAY = 0.5 V, V
CC
= 12 V to 6.9 to 12
V, Ramp PGDELAY to 0.1 V, Monitor I
(PGDELAY)
With 0.01
mF.
Note 3
0.1
0.25
0.3
V
Test Conditions
Min
Typ
Max
Unit
“Good” Signal Delay
PWM Comparator
PWM Comparator Offset
Ramp Max Duty Cycle
Artificial Ramp
Transient Response
V
FB
Input Range
Oscillator
Switching Frequency
General Electrical Specifications
V
CC
Supply Current
Start Threshold
Stop Threshold
Hysteresis
1.0
3.0
5.0
ms
V
FB
= 0 V, Increase COMP Until GATE(H)
Starts Switching
−
Duty Cycle = 50%
COMP = 1.5 V, V
FB
20 mV Overdrive. Note 3
Note 3
0.475
−
18
−
0
0.525
80
25
200
−
0.575
−
35
300
1.4
V
%
mV
ns
V
−
150
200
250
kHz
COMP = 0 V (No Switching)
GATE(H) Switching, COMP Charging
GATE(H) Not Switching, COMP Discharging
Start − Stop
−
8.0
7.0
0.75
10
8.5
7.5
1.0
15
9.0
8.0
1.25
mA
V
V
V
3. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
1
2
3
4
PIN SYMBOL
V
CC
PWRGD
PGDELAY
COMP
Power supply input.
Open collector output goes low when V
FB
is out of regulation. User must externally
limit current into this pin to less than 20 mA.
External capacitor programs PWRGD low−to−high transition delay.
Error amp output. PWM comparator reference input. A capacitor to LGND provides
error amp compensation and Soft−Start. Pulling pin < 0.475 V locks gate outputs to a
zero percent duty cycle state.
High−side switch FET driver pin. Capable of delivering peak currents of 1.5 A.
Low−side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A.
Error amplifier and PWM comparator input.
Power supply return.
FUNCTION
5
6
7
8
GATE(H)
GATE(L)
V
FB
GND
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NCP1571
Fault Latch
S
+
+
−
−
8.5 V/7.5 V
+
+
−
0.25 V
R
Set Dominant
Q
V
CC
−
UVLO COMP
GND
V
CC
Error Amp
−
+
+
+
−
0.980 V
S
Reset Dominant
COMP
0.525 V
− +
Σ
OSC
GATE(L)
Non
Overlap
V
FB
−
PWM COMP
PWM Latch
R
Q
GATE(H)
Art Ramp
80%, 200 kHz
+
−
+
−
12
mA
PGDELAY
0.25 V
−
+
+
−
0.88 V/0.69 V
PGDELAY Latch
S
Q
+
−
−
+
PWRGD
3.3 V
R
Set Dominant
Figure 2. Block Diagram
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