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HY62QF8100CLLF-85

产品描述Standard SRAM, 128KX8, 85ns, CMOS, PBGA48, FINE PITCH, BGA-48
产品类别存储    存储   
文件大小155KB,共9页
制造商SK Hynix(海力士)
官网地址http://www.hynix.com/eng/
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HY62QF8100CLLF-85概述

Standard SRAM, 128KX8, 85ns, CMOS, PBGA48, FINE PITCH, BGA-48

HY62QF8100CLLF-85规格参数

参数名称属性值
厂商名称SK Hynix(海力士)
零件包装代码BGA
包装说明TFBGA,
针数48
Reach Compliance Codeunknown
ECCN代码EAR99
最长访问时间85 ns
JESD-30 代码R-PBGA-B48
JESD-609代码e1
长度6.3 mm
内存密度1048576 bit
内存集成电路类型STANDARD SRAM
内存宽度8
功能数量1
端子数量48
字数131072 words
字数代码128000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织128KX8
封装主体材料PLASTIC/EPOXY
封装代码TFBGA
封装形状RECTANGULAR
封装形式GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度1.1 mm
最大供电电压 (Vsup)2.7 V
最小供电电压 (Vsup)2.3 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层TIN SILVER COPPER
端子形式BALL
端子节距0.75 mm
端子位置BOTTOM
宽度6.2 mm
Base Number Matches1

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HY62QF8100C Series
128Kx8bit full CMOS SRAM
DESCRIPTION
The HY62QF8100C is a high speed, super low
power and 1M bit full CMOS SRAM organized as
131,072 words by 8bit. The HY62QF8100C uses
high performance full CMOS process technology
and designed for high speed low power circuit
technology. It is particularly well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 1.2V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(LL/SL-part)
- 1.2V(min) data retention
Standard pin configuration
-. 48 - FBGA
-. 32 - sTSOPI - 8X13.4(Standard)
Product
Voltage
Speed
No.
(V)
(ns)
HY62QF8100C
2.3~2.7 70/85/100
HY62QF8100C-I
2.3~2.7 70/85/100
Note 1. Blank : Commercial, I : Industrial
2. Current value is max.
Operation
Current/Icc(mA)
3
3
Standby Current(uA)
LL
SL
3
1
3
1
Temperature
°C
0~70
-40~85(I)
PIN CONNECTION
A0
A1
CS2 A3
/WE A4
NC
A5
A6
A7
A8
IO1
IO2
Vcc
Vss
NC
NC
IO3
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A16
A1
A2
A3
/CS1
CS2
A0
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
I/O1
IO5 A2
IO6
Vss
Vcc
IO7
ADD INPUT
BUFFER
BUFFER
COLUMN
DECODER
MEMORY ARRAY
128K x 8
WRITE DRIVER
IO8 /OE /CS1 A16 A15 IO4
A9
A10 A11 A12 A13 A14
I/O8
CONTROL
LOGIC
FBGA
sTSOP l
/OE
/WE
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Pin Name
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Address Inputs
Data Inputs / Outputs
Power( 2.3V~2.7V)
Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Jun. 00
Hyundai Semiconductor

 
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