73M2901CE
V.22bis Single Chip Modem
Simplifying System Integration™
DS_2901CE_031
DESCRIPTION
The 73M2901CE low speed modem integrates a
data pump, controller, and analog front end in a
3.3 V device with a powerful "AT" command host
interface. The modem reduces external
component count/cost by incorporating many
features like parallel phone detect, Line-In-Use
and Ring detection in software without requiring
additional components.
The device is a "one chip fits all” solution for
applications including set-top boxes, point-of-sale
terminals, automatic teller machines, utility
meters, vending machines and smart card
readers.
Another distinctive feature of this device is pin
compatibility with Teridian’s flagship embedded
hard modems, the 73M2901CL, and the
73M1903 soft modem AFE. This offers
customers a cost effective method to design for
both hard or soft modem solutions in the same
system as a risk-free cost reduction path.
Complete support, modem reference designs
and error correction software are part of the
solution offered by Teridian. Our in-house
application engineering team is here to help
meet your international certification needs.
FEATURES
•
•
•
•
True one chip solution for embedded systems
As low as 9.5 mA operating with standby and
power down mode available
Power supply operation from 3.6 V to 2.7 V
Data modes and speeds:
V.22bis – 2400 bps
V.22/Bell212 – 1200 bps
V.21/Bell103 – 300 bps
V.23 – 1200/75 bps (with PAVI turnaround)
Bell202 – 1200 bps
Bell202/V23 1200 bps FDX 4-wire operation
V.22/Bell 212A/V.22bis synchronous modes
International Call Progress support:
FCC part 68, CTR21, JATE, etc.
DTMF generation and detection
Worldwide Caller ID capability
U.S. Type I and II support
EIA 777A compliant
SIA-2000 compliant
SMS messaging support
On chip hybrid driver
Blacklisting capability
Line-In-Use and Parallel Pick-Up (911) detection
with voltage or low cost energy detection method
Incoming ring energy detection through CID
path; no optocoupler circuitry required
Manufacturing Self Test capability
Backward compatible with 73M2901CL
Packaging: 32 lead QFN, 32-pin TQFP
DATA SHEET
January 2010
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Rev. 3.4
© 2010 Teridian Semiconductor Corporation
1
73M2901CE Data Sheet
DS_2901CE_031
Table of Contents
1
Hardware Description .................................................................................................................... 4
1.1
Power Supply ....................................................................................................................... 4
1.2
Low Power Mode .................................................................................................................. 4
1.3
Analog Line / Hybrid Interface ............................................................................................... 4
1.4
Interrupt Pins ........................................................................................................................ 4
1.5
Crystal Oscillator................................................................................................................... 5
1.5.1 Specifying a Crystal ..................................................................................................... 5
1.6
Reset .................................................................................................................................... 5
1.7
Asynchronous and Synchronous Serial Data Interface .......................................................... 5
2
Pinout ............................................................................................................................................. 6
3
Pin Descriptions ............................................................................................................................ 7
3.1
Power Pins ........................................................................................................................... 7
3.2
Analog Interface Pins ............................................................................................................ 7
3.3
Digital Interface Pins ............................................................................................................. 7
3.4
External Interrupt Pins .......................................................................................................... 8
3.5
Oscillator Pins....................................................................................................................... 8
4
Electrical Specifications................................................................................................................ 9
4.1
Absolute Maximum Ratings................................................................................................... 9
4.2
Recommended Operating Conditions.................................................................................... 9
4.3
Receiver ............................................................................................................................... 9
4.4
Transmitter ......................................................................................................................... 10
4.5
Maximum Transmit Level .................................................................................................... 10
4.6
DC Characteristics, Vcc = 3.3 V .......................................................................................... 11
4.6.1 DC Supply Current, VDD = 2.7 V (Battery EOL)......................................................... 11
4.6.2 DC Supply Current , VDD = 3.0 V .............................................................................. 11
4.6.3 DC Supply Current VDD = 3.3 V ................................................................................ 12
4.6.4 DC Supply Current VDD = 3.6 V ................................................................................ 12
5
Firmware Description .................................................................................................................. 13
5.1
Firmware Overview ............................................................................................................. 13
5.2
Firmware Features .............................................................................................................. 13
6
Design Considerations ................................................................................................................ 14
6.1
Layout Considerations ........................................................................................................ 14
6.2
73M2901CE Design Compatibility ....................................................................................... 15
6.3
Telephone Line Interface .................................................................................................... 15
6.4
Functional Considerations ................................................................................................... 16
6.4.1 SMS and V.23 Half Duplex ........................................................................................ 16
6.4.2 Leased Line Mode ..................................................................................................... 16
6.4.3 73M2901CE Energy Ring Detection .......................................................................... 17
6.4.4 Caller ID Mode Changes ........................................................................................... 18
6.4.5 Selectable Answer Tone Frequency Detection ........................................................... 18
6.4.6 73M2901CE S99 Country Code Support ................................................................... 18
7
Reference Designs ...................................................................................................................... 21
7.1
Low Cost Design Using DSP Ring and Status Monitoring .................................................... 21
7.2
Reference Design Using Traditional Hardware Line Monitoring ........................................... 22
8
Modem Performance Characteristics ......................................................................................... 23
8.1
BER versus SNR ................................................................................................................ 23
8.2
BER versus Receive Level .................................................................................................. 23
9
Package Mechanical Drawing ..................................................................................................... 24
9.1
32-Pin QFN ........................................................................................................................ 24
9.2
32-Pin TQFP....................................................................................................................... 25
10 Ordering Information ................................................................................................................... 26
11 Related Documentation ............................................................................................................... 26
12 Contact Information..................................................................................................................... 26
Revision History .................................................................................................................................. 27
2
Rev. 3.4
DS_2901CE_031
73M2901CE Data Sheet
Figures
Figure 1: 32-Pin QFN Pinout ................................................................................................................ 6
Figure 2: 32-Pin TQFP Pinout .................................................................................................................. 6
Figure 3: Low Cost Design Using DSP Ring and Status Monitoring ........................................................ 21
Figure 4: 73M2901CE Worldwide Demo Board: Daughter Board Schematic .......................................... 22
Figure 5: BER versus SNR .................................................................................................................... 23
Figure 6: BER versus Receive Level ...................................................................................................... 23
Figure 7: 32-Pin QFN Drawing ............................................................................................................... 24
Figure 8: 32-Pin TQFP Drawing ............................................................................................................. 25
Tables
Table 1: 73M2901CE QFN and TQFP Pinout........................................................................................... 6
Table 2: Leased Line Initialization Commands ....................................................................................... 16
Table 3: Approximate Thresholds for Energy Ring Detection .................................................................. 17
Table 4: 73M2901CE Order Numbers and Packaging Marks.................................................................. 26
Rev. 3.4
3
73M2901CE Data Sheet
DS_2901CE_031
1 Hardware Description
The 73M2901CE is designed to operate from a +3.6 to +2.7 volt supply with low power consumption
(~30 mW @ 3.0 volts). The modem supports automatic standby idle mode. The modem will also accept
a request to power down from the DTE via hardware control. No additional major components are
required to complete the modem core logic. The modem provides direct firmware LED support via the
port pins (pins 3, 4, 5, 6, 31, and 32).
The 73M2901 CE includes the following hardware features:
•
•
•
•
•
•
•
Fully self-contained. “AT” Command interpreter and data pump.
User pins available.
Synchronous serial data I/O available.
Asynchronous serial port.
On-chip hybrid and line driver.
Autobaud capability from 300 bps to 9600 bps.
Reduced external hardware support required with energy incoming ring detection.
1.1
Power Supply
Power is supplied to the 73M2901CE by the VPD and VPA pins. The 73M2901CE is designed for a
single +3.6 to +2.7 volt supply and for low power consumption (~30mW @ 3.0 volts). Ground is supplied
to the 73M2901CE by the VND and VNA pins.
The 73M2901CE has been designed with separated analog and digital supplies to insure the best
performance of the part by using separately filtered power supplies. It is recommended that separate
locally bypassed traces be used to apply power to the analog supply VPA and the digital supply VPD.
1.2
Low Power Mode
The Teridian 73M2901CE supports a low power standby mode. If the low power standby option is
enabled, the 73M2901CE will go into a power saving mode when idle.
While in this mode, the oscillator will be running and clocks will be supplied to the UART, timers and
interrupt blocks, but no clocks will be supplied to the CPU. Instruction processing and activity on the
internal busses is halted. Normal operation is resumed when an interruption such as assertion of
DTR
or
RING
occurs, a character is sent to the 73M2901CE TXD input, or a reset occurs.
1.3
Analog Line / Hybrid Interface
The 73M2901CE provides a differential analog output (TXAP and TXAN) and a single-ended analog input
(RXA) with internal A/D and D/A converters. A driver is provided for an internal hybrid function.
The internal hybrid driver is capable of driving an external load matching impedance and a line-coupling
transformer. The internal hybrid/line driver senses the load and adapts itself to its requirements.
The 73M2901CE provides firmware control for a hook relay driver (RELAY) as well as interrupt support
for a ring detect opto-coupler (RING).
1.4
Interrupt Pins
The external interrupt sources,
DTR
and
RING,
come from dedicated input pins of the same name.
DTR
informs the 73M2901CE that the host has requested the 73M2901CE to perform a specific function.
The function of
DTR
can be changed by “AT” commands (described in the
73M2901CE AT Command
User Guide).
4
Rev. 3.4
DS_2901CE_031
73M2901CE Data Sheet
RING
is used to inform the 73M2901CE that the external DAA circuitry or ring energy detector has
detected a ring signal. It will go active when each “RING” message is sent on RXD.
In addition, sending any character on the TXD line also generates an internal interrupt.
1.5
Crystal Oscillator
The Teridian 73M2901CE single chip modem can use an external 11.0592 MHz reference clock or can
generate a clock using only a crystal and two capacitors. If an external clock is used, it should be applied
to the OSCIN pin.
1.5.1 Specifying a Crystal
The manufacturer of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure
that the same frequency is obtained in the application, the circuit conditions must be the same.
The Teridian 73M2901CE modem requires a parallel mode (anti-resonant) crystal, the important
specifications of which are as follows:
Mode:
Frequency:
Frequency tolerance:
Temperature drift:
Load capacitance:
ESR:
Drive level:
Parallel (anti-resonant)
11.0592 MHz
±50 ppm at initial temperature
An additional ±50 ppm over full range
18 pF to 22 pF
75
Ω
max
Less than 1 mW
The peak voltage level of the oscillator should be checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins. A resistor in series with the crystal can be used, if
necessary, to reduce the oscillator’s peak voltage levels.
Crystals with low ESRs may oscillate at higher than specified voltage levels.
1.6
Reset
A reset is accomplished by holding the RESET pin high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3
µs.
At power on, the voltage at VPD, VPA, and RESET must
come up at the same time for a proper reset.
The signals
DCD, CTS
and
DSR
will be held inactive for 25 ms, acknowledging the reset operation, within
a 250 ms time window after the reset-triggering event. The 73M2901CE is ready for operation after the
250 ms window and/or after the signals
DCD, CTS
and
DSR
become active.
1.7
Asynchronous and Synchronous Serial Data Interface
The serial data interface consists of the TXD and RXD data paths (LSB shifted in and out first) and the
TXCLK and RXCLK serial synchronous clock outputs associated with the data pins;
CTS/RTS
flow
control;
DCD, DSR
and
DTR.
In asynchronous mode, the data is passed at the bit rate (tolerance is +1%,
-2.5%).
Rev. 3.4
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
