CAT9555
16-bit I
2
C and SMBus I/O
Port with Interrupt
Description
The CAT9555 is a CMOS device that provides 16−bit parallel
input/output port expansion for I
2
C and SMBus compatible
applications. These I/O expanders provide a simple solution in
applications where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9555 consists of two 8−bit Configuration ports (input or
output), Input, Output and Polarity inversion registers, and an
I
2
C/SMBus−compatible serial interface.
Any of the sixteen I/Os can be configured as an input or output by
writing to the configuration register. The system master can invert the
CAT9555 input data by writing to the active−high polarity inversion
register.
The CAT9555 features an active low interrupt output which
indicates to the system master that an input state has changed.
The three address input pins provide the device’s extended
addressing capability and allow up to eight devices to share the same
bus. The fixed part of the I
2
C slave address is the same as the
CAT9554, allowing up to eight of these devices in any combination to
be connected on the same bus.
Features
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SOIC−24
W SUFFIX
CASE 751BK
TSSOP−24
Y SUFFIX
CASE 948AR
TQFN−24
HV6 SUFFIX
CASE 510AG
TQFN−24
HT6 SUFFIX
CASE 510AN
MARKING DIAGRAMS
A3B
CAT9555WI
YMXXXX
(SOIC)
AB
CAT9555YI
3YMXXX
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
400 kHz I
2
C Bus Compatible
2.3 V to 5.5 V Operation
Low Stand−by Current
5 V Tolerant I/Os
16 I/O Pins that Default to Inputs at Power−up
High Drive Capability
Individual I/O Configuration
Polarity Inversion Register
Active Low Interrupt Output
Internal Power−on Reset
No Glitch on Power−up
Noise Filter on SDA/SCL Inputs
Cascadable up to 8 Devices
Industrial Temperature Range
24−lead SOIC and TSSOP, and 24−pad TQFN (4 x 4 mm) Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
(TSSOP)
A
= Assembly Location
3
= Matte−Tin Lead Finish
B
= Product Revision (Fixed as “B”)
CAT955W = Device Code (SOIC)
CAT9555Y = Device Code (TSSOP)
I
= Industrial Temperature Range
Y
= Production Year (Last Digit)
M
= Production Month (1−9, O, N, D)
XXX
= Last Three Digits of Assembly Lot Number
XXXX = Last Four Digits of Assembly Lot Number
HHHH
AXXX
YMCC
(TQFN)
HHHH
A
XXX
Y
M
CC
= Device Code
MAAB = HT6
LAAB = HV6
Applications
•
White Goods (dishwashers, washing machines)
•
Handheld Devices (cell phones, PDAs, digital cameras)
•
Data Communications (routers, hubs and servers)
= Assembly Location
= Last Three Digits of Assembly Lot Number
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Country Code
TH = Thailand
MY = Malaysia
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
June, 2011
−
Rev. 11
1
Publication Order Number:
CAT9555/D
CAT9555
Table 1. PIN DESCRIPTION
SOIC / TSSOP
1
2
3
4−11
12
13−20
21
22
23
24
TQFN
22
23
24
1−8
9
10−17
18
19
20
21
Pin Name
INT
A1
A2
I/O
0.0
−
I/O
0.7
V
SS
I/O
1.0
−
I/O
1.7
A0
SCL
SDA
V
CC
Function
Interrupt Output (open drain)
Address Input 1
Address Input 2
I/O Port 0.0 to I/O Port 0.7
Ground
I/O Port 1.0 to I/O Port 1.7
Address Input 0
Serial Clock
Serial Data
Power Supply
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
V
CC
with Respect to Ground
Voltage on Any Pin with Respect to Ground
DC Current on I/O
1.0
to I/O
1.7
, I/O
0.0
to I/O
0.7
DC Input Current
V
CC
Supply Current
V
SS
Supply Current
Package Power Dissipation Capability (T
A
= 25°C)
Junction Temperature
Storage Temperature
Ratings
−0.5
to +6.5
−0.5
to +5.5
±50
±20
160
200
1.0
+150
−65
to +150
Units
V
V
mA
mA
mA
mA
W
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
V
ZAP
(Note 1)
I
LTH
(Note 1)
Parameter
ESD Susceptibility
Latch−up
Reference Test Method
JEDEC Standard JESD 22
JEDEC JESD78A
Min
2000
100
Units
V
mA
1. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT9555
Table 4. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.3 V to 5.5 V; V
SS
= 0 V; T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
SUPPLIES
V
CC
I
CC
I
stbl
I
stbh
V
POR
SCL, SDA, INT
V
IL
(Note 2)
V
IH
(Note 2)
I
OL
I
L
C
I
(Note 3)
C
O
(Note 3)
A0, A1, A2
V
IL
(Note 2)
V
IH
(Note 2)
I
LI
I/Os
V
IL
V
IH
I
OL
Low level input voltage
High level input voltage
Low level output current
V
OL
= 0.5 V;
V
CC
= 2.3 V to 5.5 V (Note 4)
V
OL
= 0.7 V;
V
CC
= 2.3 V to 5.5 V (Note 4)
V
OH
High level output voltage
I
OH
=
−8
mA; V
CC
= 2.3 V (Note 5)
I
OH
=
−10
mA; V
CC
= 2.3 V (Note 5)
I
OH
=
−8
mA; V
CC
= 3.0 V (Note 5)
I
OH
=
−10
mA; V
CC
= 3.0 V (Note 5)
I
OH
=
−8
mA; V
CC
= 4.75 V (Note 5)
I
OH
=
−10
mA; V
CC
= 4.75 V (Note 5)
I
IH
I
IL
C
I
(Note 3)
C
O
(Note 3)
Input leakage current
Input leakage current
Input capacitance
Output capacitance
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 5.5 V; V
I
= V
SS
−0.5
0.7 x V
CC
8
10
1.8
1.7
2.6
2.5
4.1
4.0
−
−
−
−
−
−
8 to 20
10 to 24
−
−
−
−
−
−
−
−
−
−
0.3 x V
CC
5.5
−
−
−
−
−
−
−
−
1
−100
5
8
mA
mA
pF
pF
V
V
V
mA
Low level input voltage
High level input voltage
Input leakage current
−0.5
0.7 x V
CC
−1
−
−
−
0.3 x V
CC
5.5
1
V
V
mA
Low level input voltage
High level input voltage
Low level output current
Leakage current
Input capacitance
Output capacitance
V
OL
= 0.4 V
V
I
= V
CC
= V
SS
V
I
= V
SS
V
O
= V
SS
−0.5
0.7 x V
CC
3
−1
−
−
−
−
−
−
−
−
0.3 x V
CC
5.5
−
+1
6
8
V
V
mA
mA
pF
pF
Supply voltage
Supply current
Standby current
Standby current
Power−on reset voltage
Operating mode; V
CC
= 5.5 V;
no load; f
SCL
= 100 kHz
Standby mode; V
CC
= 5.5 V; no load;
V
I
= V
SS
; f
SCL
= 0 kHz; I/O = inputs
Standby mode; V
CC
= 5.5 V; no load;
V
I
= V
CC
; f
SCL
= 0 kHz; I/O = inputs
No load; V
I
= V
CC
or V
SS
2.3
−
−
−
−
−
135
1.1
0.75
1.5
5.5
200
1.5
1
1.65
V
mA
mA
mA
V
Parameter
Conditions
Min
Typ
Max
Unit
2. V
IL
min and V
IH
max are reference values only and are not tested.
3. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
4. Each I/Os must be externally limited to a maximum of 25 mA and each octal (I/O
0.0
to I/O
0.7
and I/O
1.0
to I/O
1.7
) must be limited to a maximum
current of 100 mA for a device total of 200 mA.
5. The total current sourced by all I/Os must be limited to 160 mA.
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CAT9555
Table 5. A.C. CHARACTERISTICS
(V
CC
= 2.3 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified) (Note 6)
Standard I
2
C
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 7)
t
F
(Note 7)
t
SU:STO
t
BUF
(Note 7)
t
AA
t
DH
T
i
(Note 7)
PORT TIMING
t
PV
t
PS
t
PH
INTERRUPT TIMING
t
IV
t
IR
Interrupt Valid
Interrupt Reset
4
4
ms
ms
Output Data Valid
Input Data Setup Time
Input Data Hold Time
100
1
200
ns
ns
ms
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
100
100
4
4.7
3.5
50
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast I
2
C
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
6. Test conditions according to “AC Test Conditions” table.
7. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall time
CMOS Input Voltages
CMOS Input Reference Voltages
Output Reference Voltages
Output Load: SDA, INT
Output Load: I/Os
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
DH
t
BUF
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
≤
10 ns
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
0.5 V
CC
Current Source: I
OL
= 3 mA; C
L
= 100 pF
Current Source: I
OL
/I
OH
= 10 mA; C
L
= 50 pF
t
HIGH
t
LOW
t
R
Figure 3. I
2
C Serial Interface Timing
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