Clock Generator for Cavium
Processors
8413S12I-100
Data Sheet
General Description
The 8413S12I-100 is a PLL-based clock generator specifically
designed for Cavium Networks Octeon II processors. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express reference clocks and the clocks for
both the Gigabit Ethernet MAC and PHY. The clock generator offers
ultra low-jitter, low-skew clock outputs, and edge rates that easily
meet the input requirements for the CN63XX and CN68XX series of
processors. The output frequencies are generated from a 25MHz
external input source or an external 25MHz parallel resonant crystal.
The industrial temperature range of the 8413S12I-100 supports
telecommunication, networking, and storage requirements.
Features
•
•
•
•
•
•
•
•
•
Ten 100MHz clocks for PCI Express, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15
output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15
output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Applications
•
•
•
•
•
•
•
•
•
Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
•
•
•
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
V
DDO_QREF
OE_REF
Pin Assignment
nc
QREF1
QREF0
V
DDO_G
V
DDO_E
V
DDO_F
OE_G
OE_E
nQE1
nQE0
nMR
QE1
QE0
QG
QF
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
nc
GND
nc
nc
nc
nc
nc
nc
nc
nc
nc
V
DDA
nc
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54
53
52
51
50
nc
V
DD
IREF
OE_D
nQD1
QD1
nQD0
QD0
V
DDO_D
V
DDO_C
nQC1
QC1
nQC0
QC0
OE_C
V
DD
GND
nc
8XXXXXX
49
48
47
8413S12I-100
46
45
44
43
42
41
40
39
38
37
V
DDO_A
PLL_SEL
V
DDO_B
CLK
OE_A
OE_B
V
DD
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nCLK
QA0
QA1
QB0
nQA0
nQA1
nQB0
QB1
72-pin, 10mm x 10mm LQFP Package
©2016 Integrated Device Technology, Inc.
1
nQB1
October 4, 2016
nc
8413S12I-100 Data Sheet
Block Diagram
nMR
Pullup
OE_A
QA0
100MHz
nQA0
QA1
nQA1
OE_B
QB0
100MHz
nQB0
QB1
nQB1
OE_C
QC0
100MHz
PLL_SEL
REF_SEL
Pullup
Pullup
nQC0
QC1
nQC1
OE_D
QD0
CLK
nCLK
Pulldown
Pullup/Pulldown
0
0
1
VCO
1
100MHz
nQD0
QD1
nQD1
OE_E
QE0
XTAL_IN
OSC
XTAL_OUT
IREF
100MHz
nQE0
QE1
nQE1
50MHz
QF
OE_G
125MHz
QG
OE_REF
QREF0
QREF1
OTE:
OE_A, OE_B, OE_C, OE_D, OE_E, OE_G, OE_REF have internal pull-up resistors.
©2016 Integrated Device Technology, Inc.
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October 4, 2016
8413S12I-100 Data Sheet
Pin Description and Pin Characteristic Tables
Table
1. Pin Descriptions
Number
1, 18, 38
11
2, 3, 4, 5, 6,
7, 8, 9, 10,
12, 13, 16,
19, 36, 37,
54, 55, 72
14,
15
17
20, 39, 53
21
22
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
41, 42
43, 44
45
46
47, 48
49, 50
51
52
56
57, 58
59, 60
61
Name
GND
V
DDA
Power
Power
Type
Description
Power supply ground.
Analog supply pin.
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Unused
No connect.
XTAL_IN,
XTAL_OUT
REF_SEL
V
DD
PLL_SEL
CLK
nCLK
OE_A
V
DDO_A
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
V
DDO_B
OE_C
QC0, nQC0
QC1, nQC1
V
DDO_C
V
DDO_D
QD0, nQD0
QD1, nQD1
OE_D
I
REF
V
DDO_E
QE0, nQE0
QE1, nQE1
OE_E
Input
Input
Power
Input
Input
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Output
Output
Power
Power
Output
Output
Input
Input
Power
Output
Output
Input
Pullup
Pullup
Pullup
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pullup
Pullup
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Input source control pin. See Table 3B. LVCMOS/LVTTL interface levels.
Core supply pins.
PLL bypass control pin. See Table 3A. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Active HIGH output enable for Bank A outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Active HIGH output enable for Bank C outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be connected
to 3.3V to use any of the HCSL outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank D outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode Q[Ax:Ex], nQ[Ax:EX] outputs.
Bank E (HCSL) output supply pin. 3.3V supply.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank E outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
©2016 Integrated Device Technology, Inc.
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October 4, 2016
8413S12I-100 Data Sheet
Number
Name
Type
Description
Active LOW Master Reset. When logic LOW, all outputs are reset causing the
true outputs Qx to go low and the inverted outputs nQx to go high. When logic
HIGH, all outputs are enabled. LVCMOS/LVTTL interface levels.
QF output supply pin (LVCMOS/LVTTL). 3.3V supply.
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
QG output supply pins (LVCMOS/LVTTL). 3.3V or 2.5V supply.
Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
Pullup
Pullup
Active HIGH output enable for Bank G output. See Table 3D.
LVCMOS/LVTTL interface levels.
Active HIGH output enable for QREF[0:1] outputs. See Table 3E.
LVCMOS/LVTTL interface levels.
Single-ended REF outputs. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
QREF[0:1] output supply pin (LVCMOS/LVTTL). 3.3V or 2.5V supply.
Continued on next page.
62
63
64
65
66
67
68
69,
70
71
nMR
V
DDO_F
QF
V
DDO_G
QG
OE_G
OE_REF
QREF0,
QREF1
V
DDO_QREF
Input
Power
Output
Power
Output
Input
Input
Output
Power
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output
Impedance
QF, QG,
QREF[0:1]
QG, QREF[0:1]
V
DDO_F
= V
DDO_G
= V
DDO_QREF
=
3.465V
V
DDO_QREF
, V
DDO_G
= 2.625V
Test Conditions
Minimum
Typical
2
51
51
15
15
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
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October 4, 2016
8413S12I-100 Data Sheet
Function Tables
Table 3A. PLL_SEL Control Input Function Table
Input
PLL_SEL
0
1 (default)
Operation
PLL Bypass
PLL Mode
Table 3B. REF_SEL Control Input Function Table
Input
REF_SEL
0
1 (default)
Clock Source
CLK, nCLK
XTAL_IN,
XTAL_OUT
Table 3C. OE_[A:E] Control Input Function Table
Input
OE_[A:E]
0
1 (default)
Outputs
Q[Ax:Ex], nQ[Ax:Ex]
High-Impedance
Enabled
Table 3D. OE_G Control Input Function Table
Input
OE_G
0
1 (default)
Outputs
QG
High-Impedance
Enabled
Table 3E. OE_REF Control Input Function Table
Input
OE_REF
0
1 (default)
Output
QREF[1:0]
High-Impedance
Enabled
©2016 Integrated Device Technology, Inc.
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October 4, 2016
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