GS6042
6G UHD-SDI/3G/HD/SD Adaptive
Cable Equalizer
Gennum Products
Key Features
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Supports data rates from 125Mb/s to 6.25Gb/s
SMPTE ST 2081 (proposed), SMPTE ST 424,
SMPTE ST 292, and SMPTE ST 259 compliant
Automatic cable equalization
Typical equalized length of Belden 1694A cable:
80m at 5.94Gb/s
210m at 2.97Gb/s
300m at 1.485Gb/s
500m at 270Mb/s
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Supports DVB-ASI at 270Mb/s
Supports MADI at 125Mb/s
Manual bypass control
Programmable carrier detect with squelch threshold
adjustment
Automatic power-down on loss of signal
Differential output supports DC-coupling from +1.2V
to +3.3V CML logic
Optional 6dB flat band gain on input
Selectable output de-emphasis: 2dB, 6dB, and 8dB
Standard EIA/JEDEC logic for control/status signals
Single +3.3V power supply operation
180mW power consumption (35mW in sleep)
Operating temperature range:
-
40ºC to +85ºC
Small footprint QFN package (4mm x 4mm)
Footprint compatible with the GS2974A, GS2974B,
GS2984, GS2994, and GS3440
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Pb-free and RoHS compliant
Description
The GS6042 is a high-speed BiCMOS device designed to
optimally equalize and restore signals received over 75Ω
coaxial cable.
The device supports data rates up to 6.25Gb/s while being
optimized for the proposed SMPTE ST 2081, as well as
SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259.
The GS6042 features DC restoration to compensate for the
DC content of SMPTE pathological signals.
The Carrier Detect output pin (CD) indicates whether an
input signal has been detected. It can be connected
directly to the SLEEP pin to enable automatic sleep on loss
of input.
A CD threshold is set via the SQ_ADJ pin, allowing the
GS6042 to distinguish between small amplitude SDI signals
and noise at the input of the device.
The equalizing and DC restore stages are disengaged and
no equalization occurs when the BYPASS pin is HIGH. This is
useful for signals launched at the signal source with low
data rates and/or slow rise/fall times.
The GS6042 features a gain selection pin (GAIN_SEL) which
can be used to compensate for 6dB flat attenuation prior to
the input of the device.
The differential output can be DC-coupled to Semtech’s
reclockers and cable drivers, as well as industry-standard
CML logic by changing the voltage applied to the
VCC_O pin. In general, DC-coupling to any termination
voltage between +1.2V and +3.3V is supported.
The GS6042 also features programmable output
de-emphasis with three user-selectable operating levels to
support long PCB traces at the output of the device.
Power consumption of the GS6042 is typically 180mW
when its output is DC-coupled at +1.2V.
The GS6042 is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant. This
component and all homogeneous subcomponents are
RoHS compliant.
Applications
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SMPTE ST 2081 (proposed), SMPTE ST 424,
SMPTE ST 292, and SMPTE ST 259 coaxial cable serial
digital interfaces
Serialized 8b/10b encoded video streams up to
6.25Gb/s
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GS6042
Final Data Sheet
PDS-060055
www.semtech.com
Rev. 3
May 2014
1 of 21
Proprietary and Confidential
SQ_ADJ
BYPASS
SLEEP
CD
VCC_A
Squelch Adjust
Carrier Detect
Mute
VCC_O
SDI
SDI
GAIN_SEL
Equalizer
DC
Restore
Output
DDO
DDO
VEE_O
OP_CTL
AGC
VEE_A
AGC
AGC
GS6042 Functional Block Diagram
Revision History
Version
3
2
ECO
019547
017789
PCN
—
—
Date
May 2014
February 2014
Changes and/or Modifications
Corrected the values for the de-emphasis levels
Converted to Final Data Sheet. Modified
Section 4.3.
Included reference to 6G SMPTE standard.
Converted to Final Data Sheet. Included information on
6.25G support. Updated Jitter characteristics. Updates
throughout.
New document
1
0
016407
012658
—
—
November 2013
June 2013
GS6042
Final Data Sheet
PDS-060055
www.semtech.com
Rev. 3
May 2014
2 of 21
Proprietary and Confidential
Contents
Key Features...........................................................................................................................................................1
Applications ...........................................................................................................................................................1
Description .............................................................................................................................................................1
Revision History ....................................................................................................................................................2
1. Pin Out.................................................................................................................................................................4
1.1 GS6042 Pin Assignment ...................................................................................................................4
1.2 GS6042 Pin Descriptions ..................................................................................................................4
2. Electrical Characteristics................................................................................................................................6
2.1 Absolute Maximum Ratings ...........................................................................................................6
2.2 DC Electrical Characteristics ...........................................................................................................6
2.3 AC Electrical Characteristics ............................................................................................................8
3. Input/Output Circuits.................................................................................................................................. 10
4. Detailed Description.................................................................................................................................... 11
4.1 Serial Digital Inputs ......................................................................................................................... 11
4.2 Automatic (Adaptive) Cable Equalization .............................................................................. 11
4.3 Differential Digital Data Output ................................................................................................. 11
4.4 Programmable Squelch Adjust (SQ_ADJ) ............................................................................... 12
4.5 Carrier Detect, Sleep, and Auto-Sleep ...................................................................................... 13
4.6 GAIN_SEL ............................................................................................................................................ 13
4.7 Adjustable Output Swing, De-emphasis, and Mute ........................................................... 14
5. Application Information............................................................................................................................. 16
5.1 High-Gain Adaptive Cable Equalizers ...................................................................................... 16
5.2 PCB Layout ......................................................................................................................................... 16
5.3 Typical Application Circuit ........................................................................................................... 17
6. Package & Ordering Information ............................................................................................................ 18
6.1 Package Dimensions ...................................................................................................................... 18
6.2 Packaging Data ................................................................................................................................ 18
6.3 Recommended PCB Footprint .................................................................................................... 19
6.4 Marking Diagram ............................................................................................................................. 19
6.5 Solder Reflow Profiles .................................................................................................................... 20
6.6 Ordering Information ..................................................................................................................... 20
GS6042
Final Data Sheet
PDS-060055
www.semtech.com
Rev. 3
May 2014
3 of 21
Proprietary and Confidential
1. Pin Out
1.1 GS6042 Pin Assignment
VCC_A
CD
VCC_O
13
12
16
15
SLEEP
14
VEE_A
SDI
SDI
GAIN_SEL
1
VEE_O
DDO
DDO
OP_CTL
2
3
GS6042
16-pin QFN
(top view)
11
10
4
9
5
6
7
8
AGC
AGC
Figure 1-1: GS6042 Pin Out
1.2 GS6042 Pin Descriptions
Table 1-1: GS6042 Pin Descriptions
Pin Number
1
2, 3
Name
VEE_A
SDI, SDI
Type
Power
Input
SQ_ADJ
Description
Most negative power supply connection for the input buffer, core,
and control circuits.
Connect to ground.
Serial digital differential input.
Flat Band Gain Control.
Please refer to the
DC Electrical Characteristics
table for logic level
threshold and compatibility. This pin is a +2.5V input that is tolerant
to +3.3V levels.
When HIGH, the device compensates for an additional 6dB of loss
across the entire operating band.
This pin has an internal pull-down resistor.
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External AGC capacitor connection.
EQ Bypass Control.
Please refer to the
DC Electrical Characteristics
table for logic level
threshold and compatibility. This pin is a +2.5V input that is tolerant
to +3.3V levels.
Forces the equalizer and DC-restore stages into Bypass mode when
HIGH. No equalization occurs in this mode.
This pin has an internal pull-down resistor.
4
GAIN_SEL
5, 6
AGC, AGC
7
BYPASS
BYPASS
Ground Pad
(bottom of package)
Input
Input
GS6042
Final Data Sheet
PDS-060055
www.semtech.com
Rev. 3
May 2014
4 of 21
Proprietary and Confidential
Table 1-1: GS6042 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Squelch Threshold Adjust.
Adjusts the input signal amplitude threshold of the carrier detect
function. The serial data output of the device can be muted when
the serial data input signal amplitude is too low by connecting the
CD and OP_CTL pins using a suitable resistor network (see
Figure 4-4
and
Figure 4-5).
This pin has an internal pull-down resistor.
Note:
The SQ_ADJ function is only available when the device is not
configured for auto-sleep mode. Reference
Section 4.5
for more
detail.
Output Swing, De-emphasis and Mute Control.
When this pin is connected to GND, the output swing is 850mV
ppd
with no de-emphasis applied to the output signal.
9
OP_CTL
Input
With this pin connected to +2.5V, the output is muted.
Intermediate voltages and functions are shown in
Table 4-5.
These
voltages can be achieved as shown in
Figure 4-4
and
Figure 4-5.
This pin has an internal pull-down resistor.
10, 11
12
13
DDO, DDO
VEE_O
VCC_O
Output
Power
Power
Serial digital differential output.
Most negative power supply connection for the output buffer.
Connect to ground.
Most positive power supply connection for the output buffer.
Connect to 1.2V - 3.3V DC.
SLEEP Control.
Please refer to the
DC Electrical Characteristics
table for logic level
threshold and compatibility. This pin is a +2.5V input that is tolerant
to +3.3V levels.
When HIGH the part is powered-down except for the Carrier Detect
function.
14
SLEEP
Input
This pin can be connected directly to the CD pin to automatically
put the device to sleep (low-power operation) on loss of carrier.
This pin has an internal pull-down resistor.
Note:
When SLEEP is connected to CD for automatic power
reduction on loss of carrier, the SQ_ADJ pin will not modify the CD
threshold. The CD threshold will revert to the default value used
when SQ_ADJ is pulled LOW.
Carrier Detect Status Output.
15
CD
Output
Please refer to the
DC Electrical Characteristics
table for logic level
threshold and compatibility. This pin is a +2.5V output.
Indicates presence of an input signal. When the CD pin is LOW, a
signal has been detected at the input. When this pin is HIGH, this
indicates loss of input signal.
16
VCC_A
Power
Most positive power supply connection for the input buffer, core
and control circuits.
Connect to +3.3V DC.
—
Center Pad
Power
Internally bonded to VEE_A.
Connect to GND with at least 5 vias.
8
SQ_ADJ
Input
GS6042
Final Data Sheet
PDS-060055
www.semtech.com
Rev. 3
May 2014
5 of 21
Proprietary and Confidential
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