UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L2568 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62L2568 is designed for very low power
system applications. It is particularly well suited for
battery back-up nonvolatile memory applications.
It operates from a wide range of 2.5V~ 3.6V supply
voltage. Easy memory expansion is provided by
using two chip enable input (
CE
1
,CE2). And all
inputs and three-state outputs are fully TTL
compatible.
UT62L2568(I)
FEATURES
Fast access time :
55ns(max.) for Vcc=2.7V~3.6V
70ns(max.) for Vcc=2.5V~3.6V
CMOS Low operating power
Operating : 40/25mA (Icc max.)
Standby : T
A
=0
℃
~50
℃
20 uA(max.) L -version
3 uA(max.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Industrial : -40
℃
~85
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Package : 32-pin 8mm x 20mm TSOP-
Ⅰ
32-pin 8mm x 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
256K
×
8
MEMORY
ARRAY
A0-A17
DECODER
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80082
1
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568(I)
PIN CONFIGURATION
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
B
C
D
E
F
G
H
A0
I/O5
I/O6
Vss
Vcc
I/O7
I/O8
A9
A1
A2
CE2
WE
A3
A4
A5
A6
A7
A8
I/O1
I/O2
Vcc
Vss
A10
CE1
OE
NC
UT62L2568
NC
OE
A10
CE1
A11
A17
A16
A12
A15
A13
I/O3
I/O4
A14
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
TSOP-1 / STSOP
1
2
3
4
5
6
TFBGA
PIN DESCRIPTION
SYMBOL
A0 - A17
I/O1 - I/O8
CE1 ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80082
2
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568(I)
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE
1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION SUPPLY CURRENT
High - Z
High -Z
High - Z
D
OUT
D
IN
I
SB
,
I
SB1 ,
I
SB2
I
SB
,
I
SB1
, I
SB2
I
CC ,
Icc1 , Icc2
I
CC,
Icc1 , Icc2
I
CC,
Icc1 , Icc2
H = V
IH
, L=V
IL
, X = Don't care.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to Vcc+0.3V
-40 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.6V, T
A
= -40
℃
to 85
℃
)
PARAMETER
SYMBOL
TEST CONDITION
Power Voltage
Vcc
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current
I
LO
V
SS
≦
V
I/O
≦
V
CC,
Output Disabled
Output High Voltage
V
OH
I
OH
= - 1mA
Output Low Voltage
V
OL
I
OL
= 2.1mA
Cycle time=Min.100% duty,
55
I
CC
70
CE
1
=V
IL
, CE2 = V
IH
, I
I/O
=0mA
Cycle time = 1µs,100% duty,
Icc
1
CE
1
≦
0.2V,CE2
≧
V
CC
-0.2V, I
I/O=
0mA,
Operating Current
other pins at 0.2V or Vcc-0.2V,
Cycle time =500ns,100% duty,
Icc
2
CE
1
≦
0.2V,CE2
≧
V
CC
-0.2V, I
I/O=
0mA,
other pins at 0.2V or Vcc-0.2V,
Standby Current (TTL)
I
SB
CE
1
=V
IH
or CE2 = V
IL
I
SB1
Standby Current (CMOS)
I
SB2
CE
1
≧
V
CC
-0.2V or
.CE2
≦
0.2V,
other pins at 0.2V or Vcc-0.2V,
T
A
=0
℃
~50
℃
CE
1
≧
V
CC
-0.2V or
.CE2
≦
0.2V,
other pins at 0.2V or Vcc-0.2V,
T
A
= - 40
℃
~85
℃
-L
-LL
-L
-LL
MIN. TYP. MAX. UNIT
2.5 3.0
3.6
V
2.2
-
Vcc+0.3 V
- 0.3
-
0.6
V
-1
-
1
µA
-1
-
1
µA
2.2
-
-
V
-
-
0.4
V
-
25
40
mA
-
15
25
mA
-
4
5
mA
-
-
-
-
-
-
8
0.3
-
-
-
-
10
0.5
20
3
80
10
mA
mA
µA
µA
µA
µA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80082
3
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568(I)
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3V
5ns
1.5V
C
L
= 30pF+1TTL, I
OH
= -1mA, I
OL
= 2.1mA
AC ELECTRICAL CHARACTERISTICS
( T
A
= - 40
℃
to 85
℃
)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYMBOL
t
RC
t
AA
t
ACE1,
t
ACE2
t
OE
t
CLZ1*,
t
CLZ2*
t
OLZ*
t
CHZ1*,
t
CHZ2*
t
OHZ*
t
OH
UT62L2568-55
V
CC
= 2.7V~3.6V
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UT62L2568-70
V
CC
= 2.5V~3.6V
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
t
WC
t
AW
t
CW1,
t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
UT62L2568-55
V
CC
= 2.7V~3.6V
MIN.
MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
30
UT62L2568-70
V
CC
= 2.5V~3.6V
MIN.
MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
30
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80082
4
UTRON
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UT62L2568(I)
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
tR
C
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
1
, CE2 and
OE
Controlled)
(1,3,5,6)
t
RC
Address
CE1
t
ACE1
t
AA
CE2
t
ACE2
OE
t
CLZ1
t
CLZ2
Dout
HIGH-Z
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ1
t
CHZ2
HIGH-Z
Data Valid
Notes :
WE
is HIGH for a read cycle.
2. Device is continuously selected
OE
,
CE
1
=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
CE
1
low and CE2 high transition; otherwise t
AA
is the limiting parameter.
4.
6.
OE
is low.
Transition is measured
±500mV
from steady state.
At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF.
1.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80082
5
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