Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
-
Utilizes industry standard 8M X 16 DDR Synchronous DRAMs
in TSOP package , industry standard EEPROM(SPD) in
TSSOP package
-
200pin SO-DIMM
-
Vdd=Vddq=2.5v ±0.2V
DESCRIPTION
The MH8D64AKQC is 8388608 - word x 64-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 4 industry standard 8M x 16 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
-
DLL aligns DQ and DQS transitions with CLK transition edges of DQS
FEATURES
Max.
Frequency
CLK
Access Time
[component level]
Type name
MH8D64AKQC-75
MH8D64AKQC-10
133MHz
100MHz
+ 0.75ns
+ 0.8ns
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address
,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-8
- SSTL_2 Interf ace
- Module 1bank Conf igration
APPLICATION
Main memory unit for Note PC, Mobile etc.
PCB Outline
(Front)
(Back)
1
2
199
200
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
1
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN
NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
PIN
NAME
Vref
Vss
DQ0
DQ1
Vdd
DQS0
DQ2
Vss
DQ3
DQ8
Vdd
DQ9
DQS1
Vss
DQ10
DQ11
Vdd
CK0
/CK0
Vss
DQ16
DQ17
Vdd
DQS2
DQ18
Vss
DQ19
DQ24
Vdd
DQ25
DQS3
Vss
DQ26
DQ27
Vdd
NC
NC
Vss
NC
NC
Vdd
NC
PIN
NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
PIN
NAME
Vref
Vss
DQ4
DQ5
Vdd
DM0
DQ6
Vss
DQ7
DQ12
Vdd
DQ13
DM1
Vss
DQ14
DQ15
Vdd
Vdd
Vss
Vss
DQ20
DQ21
Vdd
DM2
DQ22
Vss
DQ23
DQ28
Vdd
DQ29
DM3
Vss
DQ30
DQ31
Vdd
NC
NC
Vss
NC
NC
Vdd
NC
PIN
NO.
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
PIN
NAME
NC
Vss
CK2
/CK2
Vdd
CKE1
NC
A12
A9
Vss
A7
A5
A3
A1
Vdd
A10/AP
BA0
/WE
/S0
NC
Vss
DQ32
DQ33
Vdd
DQS4
DQ34
Vss
DQ35
DQ40
Vdd
DQ41
DQS5
Vss
DQ42
DQ43
Vdd
Vdd
Vss
Vss
DQ48
DQ49
Vdd
PIN
NO.
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
PIN
NAME
NC
Vss
Vss
Vdd
Vdd
CKE0
NC
A11
A8
Vss
A6
A4
A2
A0
Vdd
BA1
/RAS
/CAS
/S1
NC
Vss
DQ36
DQ37
Vdd
DM4
DQ38
Vss
DQ39
DQ44
Vdd
DQ45
DM5
Vss
DQ46
DQ47
Vdd
/CK1
CK1
Vss
DQ52
DQ53
Vdd
NC: No Connect
PIN
NO.
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
PIN
NAME
DQS6
DQ50
Vss
DQ51
DQ56
Vdd
DQ57
DQS7
Vss
DQ58
DQ59
Vdd
SDA
SCL
VddSPD
VddID
PIN
NO.
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PIN
NAME
DM6
DQ54
Vss
DQ55
DQ60
Vdd
DQ61
DM7
Vss
DQ62
DQ63
Vdd
SA0
SA1
SA2
NC
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
/S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
22Ω
LDQS
LDM
/S
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
/S
UDQS
UDM
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS
LDM
/S
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D2
2
3
4
5
6
7
/S
UDQS
UDM
8
9
10
11
12
13
14
15
/S
LDQS
LDM
LDQS
LDM
UDQS
UDM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SERIAL PD
UDQS
UDM
CKE0
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
VddSPD
Vref
Vdd
Vss
VddID
D0 - D3
D0
D0
D0
D0
-
-
-
-
D3
D3
D3
D3
CK0
/CK0
CK1
/CK1
CK2
/CK2
2loads SCL
SA0
SA1
2loads SA2
A0
A1
A2
SDA
WP
0loads
NOTE: DQ wiring may differ from that
described in this drawing; however
DQ/DM/DQS relationships are
maintained as shown.
Vdd ID strap connections:
(for memory device Vdd, VddQ)
Strap out (open): Vdd=VddQ
Strap in (closed): Vdd=VddQ
SPD
D0 - D3
D0 - D3
D0 - D3
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
3
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CK0-2 and /CK0-2 are dif f erential clock inputs. All address and control
input signals are sampled on the crossing of the positiv e edge of CK0-2 and
negativ e edge of /CK0-2. Output (read) data is ref erenced to the crossings of
CK0-2 and /CK0-2 (both directions of c rossing).
Clock Enable: CKE0-1 controls internal clock. When CKE0-1 is low, internal
clock f or the f ollowing cy c le is ceased. CKE0-1 is also used to select auto /
self ref resh. After self ref resh mode is started, CKE0-1 becomes
asy nchronous input. Self ref resh is maintained as long as CKE0-1 is low.
Chip Select: When /S0-1 is high, any command means No Operation.
CK0-2,/CK0-2
Input
CKE0
Input
/S0
/RAS, /CAS, /WE
Input
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-11. The Column Address is specif ied by A0-8.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
Bank Address: BA0-1 specif y one of f our banks in SDRAM to which a command
is applied. BA0-1 must be set with ACT, PRE, READ, WRITE commands.
A0-11
Input
BA0-1
DQ 0-64
DQS0-7
Input
Input / Output Data Input/Output: Data bus
Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM0-7 is
sampled HIGH along with that input data during a WRITE access. DM0-7 are sampled on both
edges of DQS0-7. Although DM pins are input only, the DM0-7 loading matches the DQ0-63 and
DQS0-7 loading.
DM0-7
Vdd, Vss
Vddspd
Vref
SDA
SCL
SA0-2
VddID
Input
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply
Input
Power Supply for SPD
SSTL_2 reference voltage.
This is a bidirectional pin used to transf er data into or out of the SPD EEPROM.
This signal is used to clock data into and out of the SPD EEPROM. A resistor
Input / Output
A resistor must be connected to Vdd to act as a pullup.
Input / Output
may be connected f rom the SCL to Vdd to act as a pullup.
Input
Output
Address pins used to select the Serial Presence Detect.
Vdd identif ication f lag
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
4
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH8D64AKQC provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CK0
CK0
/S0
/RAS
/CAS
/WE
CKE0
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
def ine basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge,
WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all,
PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
