FAN5069 PWM and LDO Controller Combo
September 2006
FAN5069
PWM and LDO Controller Combo
Features
■
■
■
Description
The FAN5069 combines a high-efficiency Pulse-Width-
Modulated (PWM) controller and an LDO (Low DropOut)
linear regulator controller. Synchronous rectification pro-
vides high efficiency over a wide range of load currents.
Efficiency is further enhanced by using the low-side
MOSFET’s R
DS(ON)
to sense current.
Both the linear and PWM regulator soft-start are con-
trolled by a single external capacitor, to limit in-rush cur-
rent from the supply when the regulators are first
enabled. Current limit for PWM is also programmable.
The PWM regulator employs a summing-current-mode
control with external compensation to achieve fast load
transient response and provide design optimization.
FAN5069 is offered in both industrial temperature grade
(-40°C to +85°C) as well as commercial temperature
grade (-10°C to +85°C).
■
■
■
■
■
■
■
■
■
General Purpose PWM Regulator and LDO Controller
Input Voltage Range: 3V to 24V
Output Voltage Range: 0.8V to 15V
– V
CC
– 5V
Shunt Regulator for 12V Operation
Support for Ceramic Cap on PWM Output
Programmable Current Limit for PWM Output
Programmable Switching Frequency (200KHz to
600KHz)
R
DS(ON)
Current Sensing
Internal Synchronous Boot Diode
Soft-Start for both PWM and LDO
Multi-Fault Protection with Optional Auto-restart
16-pin TSSOP Package
Applications
■
■
■
■
PC/Server Motherboard Peripherals
– V
CC_MCH
(1.5V), V
DDQ
(1.5V) and
V
TT_GTL
(1.25V)
Power Supply for
– FPGA, DSP, Embedded Controllers, Graphic Card
Processor, and Communication Processors
Industrial Power Supplies
High-Power DC-to-DC Converters
Ordering Information
Part Number
FAN5069MTCX
FAN5069EMTCX
Operating Temp. Range Pb-Free
-10°C to +85°C
-40°C to +85°C
Yes
Yes
Package
16-Lead TSSOP
16-Lead TSSOP
Packing Method
Tape and Reel
Tape and Reel
Qty./Reel
2500
2500
Note:
Contact Fairchild sales for availability of other package options.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Typical Application
R
VCC
+12V
VCC
+5V
C9
3 TO 24V
15
FAN5069
14
11
R(RAMP)
BOOT
C5
R8
EN
C3
7
4
3
2
8
SS
R4
R5
ILIM
R(T)
AGND
Q1
C4
C7
PWM
10
9
HDRV
SW
Q2
L1
PWM OUT
PWM OUT
Q3
13
12
LDRV
PGND
FB
C2
C1
C6
R1
GLDO
FBLDO
16
1
6
LDO OUT
C8
R7
R6
ULDO
CONTROL
5
COMP
R3
R2
Figure 1. Typical Application Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
2
FAN5069 PWM and LDO Controller Combo
Pin Assignment
FBLDO
R(T )
ILIM
SS
COMP
FB
EN
AGND
1
2
3
4
5
6
7
8
16
15
14
GLDO
VCC
R(RAMP)
LDRV
PGND
BOOT
HDRV
SW
FAN5069
13
12
11
10
9
Figure 2. Pin Assignment
Pin Description
Pin #
1
2
3
4
Name
FBLDO
R(T)
ILIM
SS
Description
LDO Feedback.
This node is regulated to V
REF
.
Oscillator Set Resistor.
This pin provides oscillator switching frequency adjustment. By plac-
ing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
Current Limit.
A resistor from this pin to GND sets the current limit.
Soft-Start.
A capacitor from this pin to GND programs the slew rate of the converter and the
LDO during initialization. It also sets the time by which the converter delays when restarting
after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO
is enabled when SS reaches 2.2V.
COMP.
The output of the error amplifier drives this pin.
Feedback.
This pin is the inverting input of the internal error amplifier. Use this pin, in combi-
nation with the COMP pin, to compensate the feedback loop of the converter.
Enable.
Enables operation when pulled to logic high. Toggling EN resets the regulator after a
latched fault condition. This is a CMOS input whose state is indeterminate if left open and
needs to be properly biased at all times.
Analog Ground.
The signal ground for IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
Switching Node.
Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and drain of low-side MOSFET.
High-Side Gate Drive Output.
Connect to the gate of the high-side power MOSFETs. This
pin is also monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET is turned off.
Bootstrap Supply Input.
Provides a boosted voltage to the high-side MOSFET driver.
Connect to bootstrap capacitor as shown in Figure 1.
Power Ground.
The return for the low-side MOSFET driver. Connect to the source of the low-
side MOSFET.
Low-Side Gate Drive Output.
Connect to the gate of the low-side power MOSFETs. This pin
is also monitored by the adaptive shoot-through protection circuitry to determine when the
lower MOSFET is turned off.
Ramp Resistor.
A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
VCC.
Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which draws current
when the input voltage is above 5.6V.
Gate Drive for the LDO.
Turned off (low) until SS is greater than 2.2V.
5
6
7
COMP
FB
EN
8
9
10
AGND
SW
HDRV
11
12
13
BOOT
PGND
LDRV
14
15
R(RAMP)
VCC
16
GLDO
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
3
FAN5069 PWM and LDO Controller Combo
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi-
tions for actual device operation.
(1)
Parameter
V
CC
to PGND
BOOT to PGND
SW to PGND
HDRV (V
BOOT
- – V
SW
)
LDRV
All Other Pins
Maximum Shunt Current for V
CC
Electrostatic Discharge Protection (ESD)
Level
(2)
HBM
CDM
Continuous
Transient (t < 50nS, F < 500kHz)
Min.
Max.
6.0
33.0
Unit
V
V
V
V
V
V
V
mA
kV
-0.5
-3.0
-0.5
-0.3
3.5
1.8
33.0
33.0
6.0
6.0
V
CC
+ 0.3
150
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are referenced to AGND.
2.
Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model).
Thermal Information
Symbol
T
STG
T
L
Parameter
Storage Temperature
Lead Soldering Temperature, 10 Seconds
Vapor Phase, 60 Seconds
Infrared, 15 Seconds
Min.
-65
Typ.
Max.
150
300
215
220
715
Unit
°C
°C
°C
°C
mW
°C/W
°C/W
P
D
θ
JC
θ
JA
Power Dissipation, T
A
= 25°C
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
(3)
37
100
Notes:
3. Junction-to-ambient thermal resistance,
θ
JA
, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat
sink characteristics.
Recommended Operating Conditions
Symbol
V
CC
T
A
T
J
Parameter
Supply Voltage
Ambient Temperature
Junction Temperature
Conditions
V
CC
to GND
Commercial
Industrial
Min.
4.5
-10
-40
Typ.
5.0
Max.
5.5
85
85
125
Unit
V
°C
°C
°C
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
4
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics
Unless otherwise noted, V
CC
= 5V, T
A
= 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Supply Current
I
VCC
I
VCC(SD)
I
VCC(OP)
V
SHUNT
Parameter
V
CC
Current (Quiescent)
V
CC
Current (Shutdown)
V
CC
Current (Operating)
V
CC
Voltage
(6)
Conditions
HDRV, LDRV Open
EN = 0V, V
CC
= 5.5V
EN = 5V, V
CC
= 5.0V,
Q
FET
= 20nC, F
SW
= 200kHz
Sinking 1mA to 100mA at V
CC
Pin
•
•
•
•
Min.
2.6
Typ.
3.2
200
10
Max.
3.8
400
15
5.9
Unit
mA
μA
mA
V
5.5
Under-Voltage Lockout (UVLO)
UVLO(H) Rising V
CC
UVLO Threshold
UVLO(L) Falling V
CC
UVLO Threshold
V
CC
UVLO Threshold
Hysteresis
Soft-Start
I
SS
V
SSOK
Oscillator
F
OSC
Frequency
Frequency Range
ΔV
RAMP
Ramp Amplitude
(Peak-to-Peak)
Minimum ON Time
Reference
V
REF
Reference Voltage
(Measured at FB Pin)
Current Amplifier Reference
(at SW node)
Error Amplifier
DC Gain
GBWP
S/R
I
FB
Gate Drive
R
HUP
R
HDN
R
LUP
R
LDN
HDRV Pull-up Resistor
HDRV Pull-down Resistor
LDRV Pull-up Resistor
LDRV Pull-down Resistor
Sourcing
Sinking
Sourcing
Sinking
•
•
•
•
1.8
1.8
1.8
1.2
3.0
3.0
3.0
2.0
Ω
Ω
Ω
Ω
Gain-BW Product
Slew Rate
Output Voltage Swing
FB Pin Source Current
10pF across COMP to GND
No Load
•
0.5
1
80
25
8
4.0
dB
MHz
V/μS.
V
μA
T
A
= 0°C to 70°C
T
A
= -40°C to 85°C
•
•
790
788
800
800
160
810
812
mV
mV
mV
R(RAMP) = 330KΩ
F = 200kHz
R(T) = 56KΩ
± 1%
R(T) = Open
240
160
160
0.4
200
300
200
360
240
600
KHz
KHz
KHz
V
nS.
Current
PWM Protection Enable
Threshold
10
2.2
1.2
μA
V
V
V
LDOSTART
LDO Start Threshold
4.00
3.60
4.25
3.75
0.50
4.50
4.00
V
V
V
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
