19-2555; Rev 1; 12/02
KIT
ATION
EVALU
BLE
AVAILA
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
General Description
Features
♦
Small Circuit Footprint
♦
Circuit Height < 2mm
♦
2.7V to 5.5V Input
♦
♦
♦
♦
♦
♦
♦
♦
♦
4.5V to 90V Output
No Overshoot
Accurate High-Side Current Limit
Avalanche Indicator Flag
8-Bit SPI-Compatible DAC
Compatible with External DAC
0.5% Accurate Output
Low Ripple Output (< 1mV)
Small 12-Pin, 4mm
✕
4mm Thin QFN Package
MAX1932
The MAX1932 generates a low-noise, high-voltage output
to bias avalanche photodiodes (APDs) in optical
receivers. Very low output ripple and noise is achieved by
a constant-frequency, pulse-width modulated (PWM)
boost topology combined with a unique architecture that
maintains regulation with an optional RC or LC post filter
inside its feedback loop. A precision reference and error
amplifier maintain 0.5% output voltage accuracy.
The MAX1932 protects expensive APDs against adverse
operating conditions while providing optimal bias.
Traditional boost converters measure switch current for
protection, whereas the MAX1932 integrates accurate
high-side current limiting to protect APDs under
avalanche conditions. A current-limit flag allows easy cali-
bration of the APD operating point by indicating the pre-
cise point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to
provide safe APD operation without data loss.
The output voltage can be accurately set with either
external resistors, an internal 8-bit DAC, an external
DAC, or other voltage source. Output span and offset
are independently settable with external resistors. This
optimizes the utilization of DAC resolution for applica-
tions that may require limited output voltage range, such
as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V.
Ordering Information
PART
MAX1932ETC
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C 12 Thin QFN
Applications
Optical Receivers and Modules
Fiber Optic Network Equipment
Telecom Equipment
Laser Range Finders
PIN Diode Bias Supply
Typical Application Circuit
INPUT
2.7V TO 5.5V
VIN
Pin Configuration
GATE
CS
VIN
MAX1932
COMP
APD BIAS OUTPUT
4.5V TO 90V
12
SCLK
DIN
CL
1
2
3
4
CS+
11
10
9
8
7
GND
COMP
DAC INPUTS
GATE
CS
SCLK
DIN
AVALANCHE
INDICATOR
FLAG
CL
GND
DACOUT
FB
CS+
CS-
MAX1932
FB
5
CS-
6
DACOUT
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
ABSOLUTE MAXIMUM RATINGS
VIN to GND...............................................................-0.3V to +6V
DIN, SCLK,
CS,
FB to GND ......................................-0.3V to +6V
COMP, DACOUT, GATE,
CL
to GND ...........-0.3V to (V
IN
+0.3V)
CS+, CS- to GND .................................................-0.3V to +110V
Continuous Power Dissipation (T
A
= +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= 0°C to +85°C,
unless otherwise noted.)
PARAMETER
GENERAL
Input Supply Range
V
IN
Undervoltage Lockout
Operating Supply Current
V
IN
Shutdown Supply Current
Input Resistance for CS+/CS-
Current-Limit Threshold
for CS+/CS-
Common-Mode Rejection
of Current Threshold
Gate-Driver Resistance
FB Input Bias Current
FB Voltage
FB Voltage
Temperature Coefficient
FB to COMP Transconductance
COMP Pulldown Resistance
in Shutdown
DACOUT to FB Voltage Difference
DACOUT Differential Nonlinearity
(Note 1)
DACOUT Voltage Temperature
Coefficient
DACOUT Load Regulation
Switching Frequency
GATE Maximum On-Time
f
OSC
t
ON
TCV
DACOUT
DAC code = 0F to FF hex, source or sink
50µA
-1
250
300
3
V
FB
TCV
FB
COMP = 1.5V
DAC code = 00 hex
DAC code = FF hex
DAC Code = 01 to FF hex,
DAC guaranteed monotonic
-3
-1
0.0007
+1
340
50
T
A
= +25°C
T
A
= 0°C to +85°C
CS+ = 3V to 100V
Gate high or low, I
GATE
=
±50mA
-25
V
IN
UVLO
I
IN
I
SHDN
00 hex loaded to DAC
Resistance from either pin to ground
0.5
1.80
Both rise/fall, hysteresis = 100mV
2.7
2.1
0.5
25
1
2.00
±0.005
5
10
+25
5.5
2.6
1
65
2.0
2.20
V
V
mA
µA
MΩ
V
%/V
Ω
nA
V
%/°C
200
100
+3
+1
µS
Ω
mV
LSB
%/°C
mV
kHz
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.24375 1.2500 1.25625
1.24250 1.2500 1.25750
0.0007
110
2
_______________________________________________________________________________________
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= 0°C to +85°C,
unless otherwise noted.)
PARAMETER
DIGITAL INPUTS (DIN, SCLK,
CS)
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUT (CL)
Output Low Voltage
Output High Voltage
SPI TIMING (FIGURE 5)
SCLK Clock Frequency
SCLK Low Period
SCLK High Period
Data Hold Time
Data Setup Time
CS
Assertion to SCLK
Rising Edge Setup Time
CS
Deassertion to SCLK
Rising Edge Setup Time
SCLK Rising Edge
to
CS
Deassertion
SCLK Rising Edge
to
CS
Assertion
CS
High Period
f
SCLK
t
CL
t
CH
t
DH
t
DS
t
CSS0
t
CSS1
t
CSH1
t
CSH0
t
CSW
125
125
0
125
200
200
200
200
300
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
SINK
= 1mA
I
SOURCE
= 0.5mA
V
IN
- 0.5
0.1
V
V
T
A
= +25°C
T
A
= 0°C to +85°C
-1
10
5
1.4
200
+1
0.6
V
V
mV
µA
nA
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1932
ELECTRICAL CHARACTERISTICS
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= -40°C to +85°C,
unless otherwise noted.) (Note 2)
PARAMETER
GENERAL
Input Supply Range
V
IN
Undervoltage Lockout
Operating Supply Current
V
IN
Shutdown Supply Current
Input Resistance for CS+/CS-
Current-Limit Threshold
for CS+/CS-
Gate-Driver Resistance
FB Input Bias Current
Gate high or low, I
GATE
=
±50mA
-30
V
IN
UVLO
I
IN
I
SHDN
00 hex loaded to DAC
Resistance from either pin to ground
0.5
1.80
Both rise/fall, hysteresis = 100mV
2.7
2.1
5.5
2.6
1
65
2
2.20
10
+30
V
V
mA
µA
MΩ
V
Ω
nA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_______________________________________________________________________________________
3
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= -40°C to +85°C,
unless otherwise noted.) (Note 2)
PARAMETER
FB Voltage
FB to COMP Transconductance
COMP Pulldown Resistance
in Shutdown
DACOUT to FB Voltage Difference
DACOUT Differential Nonlinearity
(Note 1)
DACOUT Load Regulation
Switching Frequency
DIGITAL INPUTS (DIN, SCLK,
CS)
Input Low Voltage
Input High Voltage
DIGITAL OUTPUT (CL)
Output Low Voltage
Output High Voltage
SPI TIMING (FIGURE 5)
SCLK Clock Frequency
SCLK Low Period
SCLK High Period
Data Hold Time
Data Setup Time
CS
Assertion to SCLK
Rising Edge Setup Time
CS
Deassertion to SCLK
Rising Edge Setup Time
SCLK Rising Edge
to
CS
Deassertion
SCLK Rising Edge
to
CS
Assertion
CS
High Period
f
SCLK
t
CL
t
CH
t
DH
t
DS
t
CSS0
t
CSS1
t
CSH1
t
CSH0
t
CSW
125
125
0
125
200
200
200
200
300
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
SINK
= 1mA
I
SOURCE
= 0.5mA
V
IN
- 0.5
0.1
V
V
1.4
0.6
V
V
f
OSC
SYMBOL
V
FB
COMP = 1.5V
DAC code = 00 hex
DAC code = FF hex
DAC Code = 01 to FF hex, DAC
guaranteed monotonic
DAC code = 0F to FF hex, source or sink
50µA
-4
-1
-1
240
CONDITIONS
MIN
1.23875
50
TYP
MAX
1.26125
200
100
+4
+1
+1
360
UNITS
V
µS
Ω
mV
LSB
mV
kHz
Note 1:
DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2:
Specifications to -40°C are guaranteed by design and not production tested.
4
_______________________________________________________________________________________
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Typical Operating Characteristics
(V
IN
= 5V, Circuit of Figure 2, T
A
=+25°C, unless otherwise noted)
MAX1932
SWITCHING WAVEFORMS
MAX1932 toc01
SWITCHING WAVEFORM WITH LC FILTER
MAX1932 toc02
STARTUP AND SHUTDOWN WAVEFORMS
MAX1932 toc03
V
LX
50V/div
V
LX
50V/div
I
L
0.05A/div
V
OUT
RIPPLE (AC-COUPLED)
V
OUT
= 90V
1μs/div
I
L
OUTPUT
VOLTAGE
0.05A/div
INPUT
CURRENT
0.002V/div
50V/div
0.002V/div
V
OUT
RIPPLE (AC-COUPLED)
V
OUT
= 90V, L = 300μH, C = 1μF, FIGURE 7
1μs/div
50mA/div
20ms/div
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX1932 toc04
VFB vs. TEMPERATURE
MAX1932 toc05
OUTPUT VOLTAGE vs. LOAD CURRENT
90
85
OUTPUT VOLTAGE (V)
80
75
70
65
60
55
50
V
CC
= 5V, INDUCTOR = 100μH,
R1 = 806Ω
FEEDBACK DIVIDER CURRENT AND CS-
CURRENT INCLUDED
0
0.5
1.0
1.5
2.0
2.5
3.0
CURRENT LIMIT
ACTIVATED
MAX1932 toc06
MAX1932 toc09
92
1.2520
1.2515
1.2510
1.2505
VFB (V)
95
OUTPUT VOLTAGE (V)
91
90
1.2500
1.2495
89
1.2490
1.2485
88
2.5
3.5
4.5
5.5
INPUT VOLTAGE (V)
1.2480
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
LOAD CURRENT (mA)
OUTPUT VOLTAGE STEP-DOWN
DUE TO DAC CHANGE
MAX1932 toc07
OUTPUT VOLTAGE STEP-UP
DUE TO DAC CHANGE
MAX1932 toc08
OUTPUT VOLTAGE STEP
DUE TO DACOUT CHANGE
OFFSET = 62.962V = 88 hex
STEP DOWN FROM 80 hex TO 88 hex
V
OUT
AT
64.233V
V
OUT
AT
1V/div 62.692V
OFFSET
OFFSET = 62.962V = 88 hex
STEP VALUE = 64.233 = 80 hex
20V/div
1V/div
DACOUT EXTERNAL SOURCE
0.5V/div
10ms/div
10ms/div
20ms/div
_______________________________________________________________________________________
5
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