HCC/HCF4031B
64-STAGE STATIC SHIFT REGISTER
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FULLY STATIC OPERATION : DC to 16MHz
(TYP.) @ V
DD
– V
SS
= 15V
STANDARD TTL DRIVE CAPABILITY ON Q
OUTPUT
RECIRCULATION CAPABILITY
THREE CASCADING MODES :
DIRECT CLOCKING FOR HIGH-SPEED
OPERATION
DELAYED CLOCKING FOR REDUCED CLOCK
DRIVE REQUIREMENTS
ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA at 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N
O
. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4031BF
HCF4031BEY
HCF4031BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4031B
(extended temperature range) and
HCF4031B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The
HCC/HCF4031B
is a static shift register that
contains 64 D-type, master-slave flip-flop stages
and one stage which is a D-type master flip-flop only
(referred to as a 1/2 stage). The logic level present
at the DATA input is transferred into the first stage
and shifted one stage at each positive-going clock
transition. Maximum clock frequencies up to 16
Megahertz (typical) can be obtained. Because fully
static operation is allowed, information can be per-
manently stored with the clock line in either the low
or high state. The
HCC/HCF4031B
has a MODE
CONTROL input that, when in the high state, allows
operation in the recirculating mode. The MODE
CONTROL input can also be used to select between
two separate data sources. Register packages can
be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock
output(CL
D
) is provided that enables cascading reg-
June 1989
1/12
HCC/HCF4031B
ister packages while allowing reduced clock drive
fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from
the 1/2 stage, which is available on the next nega-
tive-going transition of the clock after the Q output
occurs. This delayed output, like the delayed clock
CL
D
, is used with clocks having slow rise and fall
times.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
*
V
I
I
I
P
t ot
Parameter
Supply Voltage :
HC C
Types
H C F
Types
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T
o p
= Full Package-temperature Range
Operating Temperature :
HCC
Types
H CF
Types
Storage Temperature
Value
– 0.5 to + 20
– 0.5 to + 18
– 0.5 to V
DD
+ 0.5
±
10
200
100
– 55 to + 125
– 40 to + 85
– 65 to + 150
Unit
V
V
V
mA
mW
mW
°C
°C
°C
T
op
T
stg
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at theseor any other conditions abovethose indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I
T
op
Parameter
Supply Voltage :
HCC
Types
HC F
Types
Input Voltage
Operating Temperature :
H CC
Types
H C F
Types
Value
3 to + 18
3 to + 15
0 to V
DD
– 55 to + 125
– 40 to + 85
Unit
V
V
V
°C
°C
2/12
HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25°C, C
L
= 50pF, R
L
= 200kΩ,
typical temperature coefficient for all V
DD
values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
Parameter
Test Conditions
V
D D
(V)
Min.
5
10
15
5
10
15
5
10
15
t
THL ’
, t
T L H
Transition Time :
(any output, except Qt
THL
)
5
10
15
t
T HL
Q,
5
10
15
t
set up
Data Setup Time
5
10
15
t
h o ld
Data Hold Time
5
10
15
t
W
Clock Pulse Width
5
10
15
f
max
Maximum Clock Input
Frequency**
5
10
15
t
r
, t
f
Clock Input Rise or Fall Time*
5
10
15
2
5
6
Value
Typ.
250
110
90
190
80
65
100
50
40
100
50
40
50
25
20
30
15
10
30
15
10
120
50
40
4
10
12
1000
1000
200
µs
MHz
Max.
500
220
180
380
160
130
200
100
80
200
100
80
100
50
40
60
30
20
60
30
20
240
100
80
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
P HL
,
Propagation Delay Time :
t
PL H
, t
PL H
Clock to Q,
Clock to Q
t
P HL
,
Propagation Delay Time :
t
PL H
, t
PHL
Clock to Q’
Clock to Q
Clock to CL
D
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmition time of the output driving stage.
* * Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
1
fmax =
where n = nimber of packages
(n-1) CLD prop. delay + Q prop. delay + set-up time
b) Not Usng Delaye Clock :
1
fmax =
propagation delay + set-up time
5/12
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