IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
®
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMOS SyncFIFO™
64 X 9, 256 x 9, 512 x 9,
1024 X 9, 2048 X 9 and 4096 x 9
Integrated Device Technology, Inc.
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
IDT72241
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 x 9-bit organization (IDT72421)
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1024 x 9-bit organization (IDT72221)
2048 x 9-bit organization (IDT72231)
4096 x 9-bit organization (IDT72241)
12 ns read/write cycle time (IDT72421/72201/72211)
15 ns read/write cycle time (IDT72221/72231/72241)
Read and write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be set to any depth
Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance
state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and
ceramic leadless chip carrier (LCC)
For Through-Hole product please see the IDT72420/
72200/72210/72220/72230/72240 data sheet
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT72421/72201/72211/72221/72231/72241
SyncFIFO™ are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72421/72201/72211/72221/72231/72241 have a 64,
256, 512, 1024, 2048, and 4096 x 9-bit memory array,
respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks
and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and two
write enable pins (
WEN1
, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (
REN1
,
REN2
). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (
OE
) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (
EF
)
and Full (
FF
). Two programmable flags, Almost-Empty (
PAE
)
and Almost-Full (
PAF
), are provided for improved system
control. The programmable flags default to Empty+7 and Full-
7 for
PAE
and
PAF
, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (
LD
).
The IDT72421/72201/72211/72221/72231/72241 are
fabricated using IDT’s high-speed submicron CMOS
technology. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B.
LD
FUNCTIONAL BLOCK DIAGRAM
WCLK
D
0
- D
8
WEN1
WEN2
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9
FLAG
LOGIC
EF
PAE
PAF
FF
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
SyncFIFO is a trademark and
the IDT logo is a registered trademark of Integrated Device Technology, Inc.
RS
REN1
REN2
OE
Q
0
- Q
8
2655 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc
AUGUST 1993
DSC-2040/4
5.06
1
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D
7
4
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
D
8
D
2
D
3
D
4
D
5
D
6
PIN CONFIGURATION
INDEX
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
J32-1
L32-1
LCC/PLCC
TOP VIEW
23
22
21
14 15 16 17 18 19 20
EF
FF
Q
2
Q
4
Q
3
Q
0
Q
1
2655 drw 02
PIN DESCRIPTIONS
Symbol
D
0
-D
8
RS
Name
Data Inputs
Reset
WCLK
Write Clock
Write Enable 1
WEN1
WEN2/
LD
Write Enable 2/
Load
Q
0
-Q
8
RCLK
Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
REN1
REN2
OE
EF
PAE
PAF
FF
V
CC
GND
Programmable
Almost-Empty
Flag
Programmable
O
Almost-Full Flag
Full Flag
O
Power
Ground
I/O
Description
I
Data inputs for a 9-bit bus.
I
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after
power-up.
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
I
If the FIFO is configured to have programmable flags,
WEN1
is the only write enable pin.
When
WEN1
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables,
WEN1
must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the
FF
is LOW.
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD
is HIGH at reset, this pin operates as a second write enable. If WEN2/
LD
is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,
WEN1
must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the
FF
is LOW. If the FIFO is config-
ured to have programmable flags, WEN2/
LD
is held LOW to write or read the programmable flag
offsets.
O Data outputs for a 9-bit bus.
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1
and
REN2
are
asserted.
I
When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF
is LOW.
I
When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF
is LOW.
I
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a
high-impedance state.
O When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
O When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7.
PAE
is synchronized to RCLK.
When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7.
PAF
is synchronized to WCLK.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is
HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2655 tbl 01
5.06
2
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CCM
V
CCC
Parameter
Military Supply Voltage
Commercial
Supply Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Min.
4.5
4.5
0
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
2655 tbl 03
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +135
50
°C
°C
GND
V
IH
V
IH
°C
V
IL
mA
2655 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
2655 tbl 04
C
OUT
(1,2)
NOTES:
1. With output deselected (
OE
= HIGH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= -55°C to +125°C)
IDT72421
IDT72201
IDT72211
Commercial
t
CLK
= 12, 15, 20, 25,35, 50ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
–1
10
—
0.4
140
IDT72421
IDT72201
IDT72211
Military
t
CLK
= 20, 25,35, 50ns
Min.
Typ.
Max.
–10
–10
2.4
—
—
—
—
—
—
—
10
10
—
0.4
160
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2mA
Output Logic “0” Voltage, I
OL
= 8mA
Active Power Supply Current
Unit
µA
µA
V
V
mA
2655 tbl 05
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC1
(4)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2mA
Output Logic “0” Voltage, I
OL
= 8mA
Active Power Supply Current
IDT72221
IDT72231
IDT72241
Commercial
t
CLK
= 15, 20, 25, 35, 50ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
–1
10
—
0.4
160
IDT72221
IDT72231
IDT72241
Military
t
CLK
= 25, 35, 50ns
Min.
Typ.
Max.
–10
–10
2.4
—
—
—
—
—
—
—
10
10
—
0.4
180
Unit
µA
µA
V
V
mA
2655 tbl 06
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
3 & 4.
Measurements are made with outputs open. Tested at f
CLK
= 20MHz.
(3) Typical I
CC1
= 65 + (f
CLK
* 1.1/MHz) + (f
CLK
* C
L
* 0.03/MHz-pF) mA
(4) Typical I
CC1
= 80 + (f
CLK
* 2.1/MHz) + (f
CLK
* C
L
* 0.03/MHz-pF) mA
f
CLK
= 1/t
CLK.
C
L
= external capacitive load (30pF typical)
5.06
3
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to + 70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Com'l.
72421L12 72421L15
72201L12 72201L15
72211L12 72211L15
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
AF
t
AE
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(3)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(4)
Output Enable to Output Valid
Output Enable to Output in High-Z
(4)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Skew time between Read Clock &
Write Clock for Empty Flag &Full Flag
Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
—
2
12
(1)
5
5
3
0.5
3
0.5
12
12
12
—
0
3
3
—
—
—
—
5
22
83.3
8
—
—
—
—
—
—
—
—
—
—
12
—
7
7
8
8
8
8
—
—
—
2
15
(2)
6
6
4
1
4
1
15
15
15
—
0
3
3
—
—
—
—
6
28
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
72421L20
72201L20
72211L20
—
2
20
8
8
5
1
5
1
20
20
20
—
0
3
3
—
—
—
—
8
35
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
Commercial & Military
72421L25 72421L35
72201L25 72201L35
72211L25 72211L35
—
3
25
10
10
6
1
6
1
25
25
25
—
0
3
3
—
—
—
—
10
40
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
—
3
35
14
14
8
2
8
2
35
35
35
—
0
3
3
—
—
—
—
12
42
28.6
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
—
72421L50
72201L50
72211L50
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
3
50
20
20
10
2
10
2
50
50
50
—
0
3
3
—
—
—
—
15
45
20
25
—
—
—
—
—
—
—
—
—
—
50
—
28
28
30
30
30
30
—
—
Min. Max. Min. Max. Min. Max. Min. Max.
Min. Max. Min. Max.
NOTES:
2655 tbl 07
1. Valid for programmable
PAE
or
PAF
offset values
≤
7 bytes from respective boundary. With programmable
PAE
or
PAF
offset values such that
7 bytes < offset
≤
63 bytes, t
CLK
= 15ns. With programmable
PAE
or
PAF
offset values > 63 bytes, t
CLK
= 20ns.
2. Valid for programmable
PAE
or
PAF
values
≤
63 bytes from respective boundary. With programmable
PAE
or
PAF
values > 63 bytes, t
CLK
= 20ns.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5.06
4
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Commercial
Commercial and Military
72221L15
72221L20 72221L25 72221L35 72221L50
72231L15
72231L20 72231L25 72231L35 72231L50
72241L15
72241L20 72241L25 72241L35 72241L50
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable Almost-Full Flag
Read Clock to Programmable Almost-Empty Flag
Parameter
Clock Cycle Frequency
Min. Max. Min. Max.
—
2
15
(1)
6
6
4
1
4
1
15
15
15
—
0
3
3
—
—
—
—
6
28
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
—
2
20
8
8
5
1
5
1
20
20
20
—
0
3
3
—
—
—
—
8
35
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
Min. Max. Min. Max. Min. Max.
—
3
25
10
10
6
1
6
1
25
25
25
—
0
3
3
—
—
—
—
10
40
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
—
3
35
14
14
8
2
8
2
35
35
35
—
0
3
3
—
—
—
—
12
42
28.6
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
—
—
3
50
20
20
10
2
10
2
50
50
50
—
0
3
3
—
—
—
—
15
45
20
25
—
—
—
—
—
—
—
—
—
—
50
—
28
28
30
30
30
30
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
SKEW1
Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
t
SKEW2
Skew Time Between Read Clock and Write Clock
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
NOTES:
1. Valid for programmable
PAE
or
PAF
offset values
≤
511 bytes from respective boundary.
With programmable
PAE
or
PAF
offset values > 511 bytes, t
CLK
= 20ns.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
2655 tbl 08
5V
1.1K
D.U.T.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2655 tbl 09
680Ω
30pF*
2655 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.06
5
PCB设计
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