DATA SHEET
512MB Unbuffered SDRAM S.O.DIMM
HB52RF649DC-B (64M words
×
72 bits, 2 bank)
HB52RD649DC-B (64M words
×
72 bits, 2 bank)
Description
The HB52RF649DC, HB52RD649DC are a 64M
×
72
×
2 banks Synchronous Dynamic RAM Small Outline
Dual In-line Memory Module (S.O.DIMM), mounted 18
pieces of 256M bits SDRAM sealed in TCP package
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (PD). An outline of the products is 144-pin Zig
Zag Dual tabs socket type compact and thin package.
Therefore, they make high density mounting possible
without surface mount technology.
They provide
common data inputs and outputs.
Decoupling
capacitors are mounted beside TCP on the module
board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
•
Fully compatible with: JEDEC standard outline 8
bytes S.O.DIMM
•
144-pin Zig Zag Dual tabs socket type (dual lead out)
PCB height: 33.02mm (1.30inch)
Lead pitch: 0.80mm
•
3.3V power supply
•
Clock frequency: 133MHz/100MHz (max.)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed /RAS
•
4 Banks can operates simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8
•
2 variations of burst sequence
Sequential
Interleave
•
Programmable /CE latency (CL): 2, 3
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current
: HB52RF649DC-xxBL (L-version)
: HB52RD649DC-xxBL (L-version)
Document No. E0223H30 (Ver. 3.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52RF649DC-B, HB52RD649DC-B
Ordering Information
Part number
HB52RF649DC-75B*
HB52RF649DC-75BL*
1
HB52RD649DC-A6B*
1
HB52RD649DC-A6BL*
1
1
Clock frequency
MHz (max.)
133 MHz
133 MHz
100 MHz
100 MHz
/CE latency
3
3
2, 3
2, 3
Package
144-pin S.O.DIMM
Contact pad
Gold
Mounted devices
256M bits SDRAM TCP*
2
Notes: 1. 100MHz operation at /CE latency = 2.
2. Please refer to the TSOP products HM5225XX5B datasheet (E0082H) for detail information.
Pin Configurations
Front Side
1pin
2pin
59pin
60pin
61pin
62pin
143pin
144pin
Back Side
Front side
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
Pin name
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
DQMB0
DQMB1
VCC
A0
A1
A2
VSS
Pin No.
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
Pin name
NC
VSS
CB2
CB3
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
Back side
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Pin name
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQMB4
DQMB5
VCC
A3
A4
A5
VSS
Pin No.
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
Pin name
CK1
VSS
CB6
CB7
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
Data Sheet E0223H30 (Ver. 3.0)
2
HB52RF649DC-B, HB52RD649DC-B
Front side
Pin No.
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Pin name
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
CB0
CB1
CK0
VCC
/RE
/W
/S0
/S1
Pin No.
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin name
A9
A10 (AP)
VCC
DQMB2
DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
Back side
Pin No.
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Pin name
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
CB4
CB5
CKE0
VCC
/CE
CKE1
A12
NC
Pin No.
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin name
BA1
A11
VCC
DQMB6
DQMB7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
Pin Description
Pin name
A0 to A12
Function
Address input
Row address
Column address
A0 to A12
A0 to A9
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/S0, /S1
/RE
/CE
/W
DQMB0 to DQMB7
CK0, CK1
CKE0, CKE1
SDA
SCL
VCC
VSS
NC
Bank select address
Data-input/output
Check bit (Data-input/output)
Chip select
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
No connection
Data Sheet E0223H30 (Ver. 3.0)
3
HB52RF649DC-B, HB52RD649DC-B
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
6
7
8
9
1
Function described
Number of bytes used by module
manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest /CE latency)
(-75) 7.5ns
(-A6) 10ns
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
80
08
04
0D
0A
02
48
00
01
75
A0
54
60
02
82
08
08
01
0F
04
06
01
01
00
0E
A0
Comments
128
256byte
SDRAM
13
10
2
72
0 (+)
LVTTL
CL = 3
10
SDRAM access from Clock (highest
/CE latency)
0
(-75) 5.4ns
(-A6) 6ns
0
0
1
0
0
0
0
0
0
0
0
0
0
1
11
12
13
14
15
16
17
18
19
20
21
22
23
Module configuration type
Refresh rate/type
SDRAM width
Error checking SDRAM width
SDRAM device attributes:
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes: number of
banks on SDRAM device
SDRAM device attributes:
/CE latency
SDRAM device attributes:
/S latency
SDRAM device attributes:
/W latency
SDRAM module attributes
SDRAM device attributes: General
SDRAM cycle time
(2nd highest /CE latency)
10ns
SDRAM access from Clock (2nd
highest /CE latency)
6ns
SDRAM cycle time
(3rd highest /CE latency)
Undefined
ECC
Normal
(7.8125µs)
Self refresh
×
8
×
8
1 CLK
1, 2, 4, 8
4
2, 3
0
0
Unbuffer
VCC ± 10%
CL = 2
24
0
1
1
0
0
0
0
0
60
25
0
0
0
0
0
0
0
0
00
Data Sheet E0223H30 (Ver. 3.0)
4
HB52RF649DC-B, HB52RD649DC-B
Byte No.
26
27
28
Function described
SDRAM access from Clock (3rd
highest /CE latency)
Undefined
Minimum row precharge time
Row active to row active min
(-75)
(-A6)
29
30
/RE to /CE delay min
Minimum /RE pulse width
(-75)
(-A6)
31
32
Density of each bank on module
Address and command signal input
setup time
(-75)
(-A6)
33
Address and command signal input
hold time
(-75)
(-A6)
34
Data signal input setup time
(-75)
(-A6)
35
Data signal input hold time
(-75)
(-A6)
36 to 61
62
63
Superset information
SPD data revision code
Checksum for bytes 0 to 62
(-75)
(-A6)
64
65 to 71
72
73
74
75
76
77
78
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
(-75)
(-A6)
79
80
81
82
83
84
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
×
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
×
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
×
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
0
×
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
×
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
×
0
0
1
0
0
1
1
1
1
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
×
0
1
0
1
1
1
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
×
0
0
1
0
0
0
0
0
0
1
0
1
1
00
14
0F
14
14
2D
32
40
15
20
08
10
15
20
08
10
00
12
5D
C4
07
00
××
48
42
35
32
52
46
44
36
34
39
44
43
2D
*
2
(ASCII-8bit code)
H
B
5
2
R
F
D
6
4
9
D
C
20ns
15ns
20ns
20ns
45ns
50ns
256M byte
1.5ns
2.0ns
0.8ns
1.0ns
1.5ns
2.0ns
0.8ns
1.0ns
Future use
Rev. 1.2B
93
196
HITACHI
Comments
Data Sheet E0223H30 (Ver. 3.0)
5
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