Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -55°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θ
JA
)…….29°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
PARAMETER
(V
AVDD
= 3.6V, V
AVSS
= 0V, V
DVDD
= 2.0V to 3.6V, V
REFP
- V
REFN
= V
AVDD
, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)(Note 2)
SYMBOL
CONDITIONS
PGA gain of
128, single-cycle
mode at 1ksps
data rate
Noise Voltage
(Referred to Input)
PGA gain of 128,
single-cycle
mode at 12.8ksps
data rate
PGA gain of 128,
continuous
mode at 64ksps
data rate
Integral Nonlinearity
Zero Error
Zero Drift
Full-Scale Error
INL
Z
ERR
Z
Drift
FSE
After system full-scale
calibration (Notes 3 and 4)
After system zero-scale
calibration
PGA low-
noise mode
PGA low-
power mode
PGA low-
noise mode
PGA low-
power mode
PGA low-
noise mode
PGA low-
power mode
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Single-Cycle Conversion Mode)
0.19
0.26
0.83
1.16
0.83
1.16
3
1
50
2
15
ppm
µV
nV/°C
ppmFSR
µV
RMS
V
n
www.maximintegrated.com
Maxim Integrated
│
2
MAX11254
24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz
PGA,
Delta-Sigma ADC with SPI Interface
Electrical Characteristics (continued)
(V
AVDD
= 3.6V, V
AVSS
= 0V, V
DVDD
= 2.0V to 3.6V, V
REFP
- V
REFN
= V
AVDD
, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)(Note 2)
PARAMETER
Full-Scale Error Drift
SYMBOL
FSE
Drift
DC rejection
Common-Mode Rejection
CMR
50Hz/60Hz rejection (Note 5)
DC rejection with PGA gain 64
DC rejection with PGA gain 128
AVDD, AVSS Supply Rejection
Ratio
DC rejection
PSRRA
50Hz/60Hz rejection (Note 5)
DC rejection with PGA gain 128
DC rejection
DVDD Supply Rejection Ratio
PGA
Gain Setting
Noise-Spectral Density
NSD
Low-noise mode
Low-power mode
Gain = 1
Gain = 2
Gain = 4
Gain Error, Not Calibrated
G
ERR
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Output Voltage Range
MUX
Channel-to-Channel Isolation
GENERAL-PURPOSE OUTPUTS
Resistance (On)
R
ON
I
MAX
GPO_ output current = 30mA,
GPOGND connected to AVSS
Per output
Maximum Current (On)
Total from all outputs into
GPOGND pin (Note 5)
3.5
30
90
10
Ω
mA
mA
ISO
CH-CH
DC
140
dB
VOUT
RNG
V
AVSS
+ 0.3
1
6.2
10
0.75
1.2
2
3
4.5
6
5.5
2
V
AVDD
- 0.3
V
%
128
V/V
nV/√Hz
PSRRD
50Hz/60Hz rejection (Note 5)
DC rejection with PGA gain 128
73
75
65
105
105
90
110
110
80
CONDITIONS
MIN
TYP
0.05
130
130
105
95
95
95
75
115
115
110
dB
dB
dB
MAX
UNITS
ppmFSR/°C
www.maximintegrated.com
Maxim Integrated
│
3
MAX11254
24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz
PGA,
Delta-Sigma ADC with SPI Interface
Electrical Characteristics (continued)
(V
AVDD
= 3.6V, V
AVSS
= 0V, V
DVDD
= 2.0V to 3.6V, V
REFP
- V
REFN
= V
AVDD
, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)(Note 2)
PARAMETER
SYMBOL
I
leak1
Leakage Current (Off)
I
leak3
POWER-UP DELAYS
(Note 5)
T
PUPSLP
Power-Up Time
T
PUPSBY
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Input Voltage
Range,
V
CM
= (V
AIN_P
+ V
AIN_N
)/2
Input Voltage Range (AIN_P,
AIN_N)
Differential Input Voltage
Range (AIN_P – AIN_N)
DC Input Leakage
Differential Input Conductance
Differential Input Current
Common-Mode Input
Conductance
Common-Mode Input Current
Reference Differential
Input Resistance
Reference Differential
Input Current
Input Capacitance
AIN_P, AIN_N Sampling Rate
Reference Voltage Range
(REFP, REFN)
Direct (PGA bypassed)
CMI
RNG
PGA
Direct (PGA bypassed)
V
IN(RNG)
PGA
Unipolar
Bipolar
SLEEP state enabled
Direct (PGA bypassed)
PGA enabled
Direct (PGA bypassed)
PGA enabled
Active state
STANDBY and SLEEP state
Direct (PGA bypassed)
PGA
V
AVSS
V
AVSS
+ 0.4
V
AVSS
V
AVSS
+ 0.4
0
-V
REF
±0.1
±11.6
±1
±1
±10
26
±1
2.5
0.25
4.096
(Note 6)
V
AVDD
V
AVDD
V
AVDD
- 1.3
V
AVDD
V
AVDD
- 1.3
V
REF
+V
REF
SLEEP state (full power-down)
to LDO wake-up
V
AVDD
= 2.7V, V
DVDD
= 2.0V,
CAPREG = 220nF
STANDBY state (analog blocks
powered down, LDO on) to
Active
23
45
µs
4
8
CONDITIONS
Current into the GPOGND pin
with one individual GPO_ pin
connected to 3V
Current into the GPOGND pin
with all GPO_ pins connected
to 3V
MIN
TYP
0.4
nA
13
100
MAX
UNITS
V
V
V
IN(DIFF)
I
IN_LEAK
G
DIFF
I
DIFF
G
CM
I
CM
R
REF
I
REF_PD
C
IN
CP
GAIN
f
S
V
REF(RNG)
V
nA
µA/V
nA
µA/V
nA
kΩ
nA
pF
MHz
V
www.maximintegrated.com
Maxim Integrated
│
4
MAX11254
24-Bit, 6-Channel, 64ksps, 6.2nV/√Hz
PGA,
Delta-Sigma ADC with SPI Interface
Electrical Characteristics (continued)
(V
AVDD
= 3.6V, V
AVSS
= 0V, V
DVDD
= 2.0V to 3.6V, V
REFP
- V
REFN
= V
AVDD
, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
