74LCX138
Low voltage CMOS 3 to 8 line decoder (Inverter)
with 5V tolerant inputs
Features
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■
■
■
■
■
■
■
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5V tolerant inputs
High speed:
– t
PD
= 6.7ns (Max) at V
CC
= 3V
Power down protection on inputs and outputs
Symmetrical output impedance:
– |I
OH
| = I
OL
= 24mA (Min) at V
CC
= 3V
PCI bus levels guaranteed at 24mA
Balanced propagation delays:
– t
PLH
≅
t
PHL
Operating voltage range:
– V
CC
(Opr) = 2.0V to 3.6V
Pin and function compatible with
74 series 138
Latch-up performance exceeds
500mA (JESD 17)
ESD performance:
– HBM > 2000V
(MIL STD 883 method 3015); MM > 200V
SO-16
TSSOP16
Description
The 74LCX138 is a low voltage CMOS 3 to 8 line
decoder (inverting) fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to
5V signal environment for inputs.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Order codes
Part number
74LCX138MTR
74LCX138TTR
Package
SO-16
TSSOP16
Packaging
Tape and reel
Tape and reel
July 2006
Rev 5
1/17
www.st.com
17
Contents
74LCX138
Contents
1
2
Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
2.4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
5
6
7
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
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