FAN2500 — 100 mA CMOS LDO Regulator
May 2013
FAN2500
100 mA CMOS LDO Regulator
Features
•
•
•
•
•
•
•
Ultra-Low Power Consumption
100 mV Dropout Voltage at 100 mA
25
μA
Ground Current at 100 mA
Enable / Shutdown Control
SOT23-5 package
Thermal Limiting
300 mA Peak Current
Description
The FAN2500 micropower low-dropout voltage regulator
utilizes CMOS technology to offer a new level of cost-
effective performance in mobile handsets, laptop and
notebook portable computers, and other portable
devices. Features include extremely low power consump-
tion, low shutdown current, low dropout voltage, excep-
tional loop stability able to accommodate a wide variety of
external capacitors, and a compact SOT23-5 surface-
mount package. The FAN2500 offers significant improve-
ments over older BiCMOS designs and is pin-compatible
with many popular devices. The output is thermally pro-
tected against overload.
FAN2500:
pin 4 – ADJ, allows the user to adjust the
output voltage over a wide range using an external volt-
age divider.
FAN2500-XX:
pin 4 – BYP, to which a bypass capacitor
may be connected for optimal noise performance. Output
voltage is fixed, indicated by the suffix XX.
The standard fixed output voltages available are 2.5 V,
3.0 V, and 3.3 V.
Applications
• Mobile Phones and Accessories
• Portable Cameras and Video Recorders
• Laptop, Notebook, and Palmtop Computers
Ordering Information
Part Number
FAN2500S25X
FAN2500S30X
FAN2500S33X
FAN2500SX
V
OUT
2.5
3.0
3.3
Adj.
Pin 4 Function
Bypass
Bypass
Bypass
Adjust
Top Mark
ACE
ACW
AC3
ACA
Package
SOT-23 5L
SOT-23 5L
SOT-23 5L
SOT-23 5L
Packing
Method
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel Information
Quantity
3000
Reel Size
7 inches
Width
8 mm
© 2010 Fairchild Semiconductor Corporation
FAN2500 Rev. 1.1.0
1
www.fairchildsemi.com
FAN2500 — 100 mA CMOS LDO Regulator
Block Diagram
FAN2500
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pin Configuration
Pin No.
1.
2.
3.
4.
5.
FAN2500
V
IN
GND
EN
ADJ
V
OUT
FAN2500-XX
V
IN
GND
EN
BYP
V
OUT
Pin Descriptions
Pin Name
ADJ
BYP
EN
V
IN
V
OUT
GND
Pin No.
4
4
3
1
5
2
Type
Input
Passive
Functional Description
FAN2500 Adjust
Ratio of potential divider from V
OUT
to ADJ determines output voltage
FAN2500-XX Bypass
Connect a 470 pF capacitor for noise reduction
Enable
Digital Input
0:
Shutdown V
OUT
1:
Enable V
OUT
Power In
Power Out
Power
Voltage Input
Supply voltage input
Voltage Output
Regulated output voltage
Ground
© 2010 Fairchild Semiconductor Corporation
FAN2500 Rev. 1.1.0
2
www.fairchildsemi.com
FAN2500 — 100 mA CMOS LDO Regulator
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Parameter
Power Supply Voltages
V
IN
(Measured to GND)
Enable Input (EN)
Applied Voltage (Measured to GND)
(2)
Power
Dissipation
(3)
Temperature
Junction
Lead Soldering (5 s)
Storage
Min.
0
0
Max.
7
7
Internally Limited
Unit
V
V
-65
-65
150
260
150
°C
°C
°C
4
kV
Electrostatic Discharge
(4)
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only
if Recommended Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Based upon thermally limited junction temperature:
T
J
(
max
)
– T
A
P
D
= -------------------------------
Θ
JA
4. Human Body Model is 4 kV minimum using Mil Std. 883E, method 3015.7. Machine Model is 400 V minimum using
JEDEC method A115-A.
Recommended Operating Conditions
The recommended Operating Conditions table defines the conditions for actual device operation. Recommended oper-
ating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recom-
mend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
IN
V
EN
T
J
θ
JA
θ
JC
Input Voltage Range
Enable Input Voltage
Junction Temperature
Parameter
Min.
2.7
0
-40
Nom.
Max.
6.5
V
IN
+125
Unit
V
V
°C
°C/W
°C/W
Thermal Resistance, Junction to Air
Thermal Resistance, Junction to Case
220
130
© 2010 Fairchild Semiconductor Corporation
FAN2500 Rev. 1.1.0
3
www.fairchildsemi.com
FAN2500 — 100 mA CMOS LDO Regulator
Electrical Characteristics
(5, 6)
Symbol
Regulator
I
OUT
= 100
μA
V
DO
∆V
O
∆V
REF
∆V
O(7)
I
GND
Protection
Current Limit
I
GSD
T
SH
Enable Input
V
IL
V
IH
I
IH
I
I
Logic Low Voltage
Logic High Voltage
Input Current High
Input Current Low
2.0
1.2
1.4
1
1
0.4
V
V
μA
μA
Shutdown Current
Thermal Protection Shutdown Temperature
EN = 0 V
150
Thermally Protected
1
μA
°C
Drop-Out Voltage
Output Voltage Accuracy
Reference Voltage Accuracy, Adjustable Mode
Output Voltage Accuracy, Adjustable Mode
Ground Pin Current
I
OUT
= 100 mA
I
OUT
= 50 mA
I
OUT
= 100 mA
-2
1.24
-6
1.32
2.5
50
100
4.0
75
140
2
1.40
6
50
mV
mV
mV
%
V
%
μA
Parameter
Conditions
Min.
Typ.
Max.
Units
Switching Characteristics
(5, 6)
Parameter
Enable Input
(8)
Response Time
500
μsec
Max.
Unit
Performance Characteristics
(5, 6)
Symbol
∆V
OUT
/
∆V
IN
∆V
OUT
/
V
OUT
Parameter
Line Regulation
Load Regulation
Conditions
V
IN
= (V
OUT
+ 1) to 6.5 V
I
OUT
= 0.1 to 100 mA
f = 10 Hz to 1 kHz at V
IN
,
C
OUT
= 10
μF,
C
BYP
= 0.01
μF
f > 10 kHz at V
IN
,
C
OUT
= 10
μF,
C
BYP
= 0.01
μF
f = 120 Hz at V
IN
,
C
OUT
= 10
μF,
C
BYP
= 0.01
μF
Typ.
0.3
1.0
< 7.00
Max.
Unit
%/V
2.0
%
e
N
Output Noise
μV
/ Hz
< 0.01
PSRR
Power Supply Rejection
43
dB
Notes:
5. Unless otherwise stated; T
A
= 25°C, V
IN
= V
OUT
+ 1 V, I
OUT
= 100
μA,
and V
IH
> 2.0 V.
6. Bold values indicate -40
≤
T
J
≤
125°C.
7. The adjustable version has a band-gap voltage range of 1.24 V to 1.40 V with a nominal value of 1.32 V.
8. When using repeated cycling.
© 2010 Fairchild Semiconductor Corporation
FAN2500 Rev. 1.1.0
4
www.fairchildsemi.com
FAN2500 — 100 mA CMOS LDO Regulator
Typical Performance Characteristics
Figure 3. Power Supply Rejection Ratio
Figure 4. Power Supply Rejection Ratio
Figure 5. Power Supply Rejection Ratio
Figure 6. Power Supply Rejection Ratio
Figure 7. Power Supply Rejection Ratio
Figure 8. Power Supply Rejection Ratio
© 2010 Fairchild Semiconductor Corporation
FAN2500 Rev. 1.1.0
5
www.fairchildsemi.com
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