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500-00003

产品描述Linear Voltage Regulators 5.0V 1.0A Positive
产品类别半导体    分立半导体   
文件大小79KB,共7页
制造商Parallax Inc.
官网地址https://www.parallax.com/
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500-00003概述

Linear Voltage Regulators 5.0V 1.0A Positive

500-00003规格参数

参数名称属性值
产品种类
Product Category
Bipolar Transistors - BJT
制造商
Manufacturer
Parallax Inc.
RoHSDetails
安装风格
Mounting Style
Through Hole
封装 / 箱体
Package / Case
TO-92-3
Transistor PolarityPNP
Collector- Emitter Voltage VCEO Max40 V
Collector- Base Voltage VCBO40 V
Emitter- Base Voltage VEBO5 V
Collector-Emitter Saturation Voltage250 mV
Gain Bandwidth Product fT250 MHz
最大工作温度
Maximum Operating Temperature
+ 150 C
Continuous Collector Current200 mA
DC Current Gain hFE Max300
最小工作温度
Minimum Operating Temperature
- 55 C
Pd-功率耗散
Pd - Power Dissipation
250 mW
工厂包装数量
Factory Pack Quantity
1
单位重量
Unit Weight
0.016000 oz

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2N3906
Preferred Device
General Purpose
Transistors
PNP Silicon
http://onsemi.com
Features
Pb−Free Packages are Available*
2
BASE
COLLECTOR
3
MAXIMUM RATINGS
Rating
Collector − Emitter Voltage
Collector − Base Voltage
Emitter − Base Voltage
Collector Current − Continuous
Total Device Dissipation @ T
A
= 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 60°C
Total Device Dissipation @ T
C
= 25°C
Derate above 25°C
Operating and Storage Junction
Temperature Range
Symbol
V
CEO
V
CBO
V
EBO
I
C
P
D
P
D
P
D
T
J
, T
stg
Value
40
40
5.0
200
625
5.0
250
1.5
12
−55 to +150
Unit
Vdc
Vdc
Vdc
mAdc
mW
mW/°C
mW
W
mW/°C
°C
3
STRAIGHT LEAD
BULK PACK
12
TO−92
CASE 29
STYLE 1
1
1
EMITTER
3
BENT LEAD
TAPE & REEL
AMMO PACK
2
THERMAL CHARACTERISTICS
(Note 1)
Characteristic
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Symbol
R
qJA
R
qJC
Max
200
83.3
Unit
°C/W
°C/W
2N
3906
ALYWG
G
MARKING DIAGRAM
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Indicates Data in addition to JEDEC Requirements.
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2007
1
March, 2007 − Rev. 3
Publication Order Number:
2N3906/D

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