19-3772; Rev 1; 10/05
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
General Description
The MAX6880–MAX6883 dual-/triple-voltage monitors
are designed to sequence power supplies during
power-up condition. When all of the voltages exceed
their respective thresholds, these devices turn on volt-
ages to the system sequentially, enhancing n-channel
MOSFETs used as switches. The time between each
sequenced voltage is determined by an external
capacitor, thus allowing flexibility in delay timing. The
MAX6880/MAX6881 sequence three voltages and the
MAX6882/MAX6883 sequence two voltages.
These devices initially monitor all of the voltages and
when all of them are within their tolerances, the inter-
nal charge pumps enhance external n-channel
MOSFETs in a sequential manner to apply the volt-
ages to the system. Internal charge pumps drive the
gate voltages 5V above the respective input voltage
thereby ensuring the MOSFETs are fully enhanced to
reduce the on-resistance.
The MAX6880–MAX6883 feature capacitor-adjustable
slew-rate control to provide controlled turn-on charac-
teristics. After all of the voltages reach 92.5% of their
final value, a power-good output (MAX6880/MAX6882)
signal is active. The power-good output (PG/RST) can
be delayed with an external capacitor to create a
power-on reset delay. After the initial power-up phase,
the MAX6880–MAX6883 continue to monitor the volt-
ages. If any of the voltages falls below its threshold, the
MOSFETs are quickly turned off and the voltages are
tracked down together. An internal 100Ω pulldown
resistor ensures that the capacitance at the MOSFET’s
source is discharged quickly. The power-good output
goes low to provide a system reset.
The MAX6880–MAX6883 are available in small 4mm x
4mm 24-pin and 16-pin thin QFN packages and speci-
fied over the -40°C to +85°C extended operating tem-
perature range.
Features
♦
Capacitor-Adjustable Power-Up Sequencing
Delay
♦
Internal Charge Pumps to Enhance External
n-Channel FETs
♦
Capacitor-Adjustable Timeout Period Power-Good
Output (MAX6880/MAX6882)
♦
Adjustable Undervoltage Lockout or
Logic-Enable Input
♦
Internal 100Ω Pulldown for Each Output to
Discharge Capacitive Load Quickly
♦
0.5V to 5.5V Nominal IN_/OUT_ Range
♦
2.7V to 5.5V Operating Voltage Range
♦
Immune to Short Voltage Transients
♦
Small 4mm x 4mm 24-Pin or 16-Pin Thin QFN
Packages
MAX6880–MAX6883
Ordering Information
PART
MAX6880ETG+
MAX6881ETE+
MAX6882ETE+
MAX6883ETE+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
24 Thin QFN
16 Thin QFN
16 Thin QFN
16 Thin QFN
PKG
CODE
T2444-4
T1644-4
T1644-4
T1644-4
+Denotes
lead-free package.
Pin Configurations
OUT2
OUT3
N.C.
TOP VIEW
18
GATE2 19
OUT1 20
GATE1 21
IN3 22
IN2 23
+
IN1 24
1
N.C.
17
16
15
14
13
12
11
10
N.C.
N.C.
TIMEOUT
SLEW
DELAY
GND
Applications
Multivoltage Systems
Networking Systems
Telecom
Storage Equipment
Servers/Workstations
MAX6880
EP*
MARGIN
9
8
7
6
EN/UV
2
ABP
3
SET3
4
SET2
4mm x 4mm THIN QFN
Selector Guide appears at end of data sheet.
*EXPOSED PADDLE CONNECTED TO GND.
Pin Configurations continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
SET1
PG/RST
5
GATE3
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
MAX6880–MAX6883
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
IN1, IN2, IN3.............................................................-0.3V to +6V
ABP .........................................-0.3V to the highest of V
IN1 -
V
IN3
SET1, SET2, SET3 ....................................................-0.3V to +6V
GATE1, GATE2, GATE3 .........................................-0.3V to +12V
OUT1, OUT2, OUT3 .................................................-0.3V to +6V
MARGIN
...................................................................-0.3V to +6V
PG/RST, EN/UV ........................................................-0.3V to +6V
DELAY, SLEW, TIMEOUT .........................................-0.3V to +6V
OUT_ Current....................................................................±50mA
GND Current.....................................................................±50mA
Input/Output Current (all pins except
OUT_ and GND) ...........................................................±20mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin 4mm x 4mm Thin QFN
(derate 16.9mW/°C above +70°C) .............................1349mW
24-Pin 4mm x 4mm Thin QFN
(derate 20.8mW/°C above +70°C) .............................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV =
MARGIN
= ABP, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Voltage on the highest of IN_ to ensure that
PG/RST is valid and GATE_ = 0
Operating Voltage Range
IN_
Voltage on the highest of IN_ to ensure the
device is fully operational
Supply Current
SET_ Threshold Range
SET_ Threshold Hysteresis
SET_ Input Current
EN/UV Input Voltage
EN/UV Input Current
EN/UV Input Pulse Width
DELAY, TIMEOUT Output Current
DELAY, TIMEOUT Threshold
Voltage
SLEW Output Current
Sequence Slew-Rate Timebase
Accuracy
Timebase/C
SLEW
Ratio
Slew-Rate Accuracy during Power-
Up and Power-Down
I
S
SR
I
CC
V
TH
V
TH_HYST
I
SET
V
EN_R
V
EN_F
I
EN
t
EN
I
D
EN/UV falling, 100mV overdrive
(Notes 2, 3)
V
CC
= 3.3V
(Note 4)
C
SLEW
= 200pF
100pF < C
SLEW
< 1nF
C
SLEW
= 200pF, V
IN_
= 5.5V (Note 4)
-50
22.5
-15
104
+50
IN1 = 5.5V, IN2 = IN3 = 3.3V, no load
SET_ falling, T
A
= +25 C
SET_ falling, T
A
= -40 °C to +85°C
SET_ rising
SET_ = 0.5V
Input rising
Input falling
1.22
-5
7
2.12
2.5
1.25
25
27.5
+15
2.88
-100
1.286
1.25
1.28
+5
o
MIN
1.4
TYP
MAX
UNITS
V
2.7
1.1
0.4925
0.4875
0.5
0.5
0.5
+100
5.5
1.8
0.5075
0.5125
mA
V
%
nA
V
µA
µs
µA
V
µA
%
kΩ
%
2
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV =
MARGIN
= ABP, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 1)
Power-Good Threshold
Power-Good Threshold Hysteresis
GATE_ Output High
GATE_ Pullup Current
V
TH_PG
V
HYS_PG
V
GOH
I
GUP
I
GD
GATE_ Pulldown Current
I
GDS
SET_ to GATE_ Delay
PG/RST Output Low
Tracking Differential Voltage Stop
Ramp
Tracking Differential Fault Voltage
Power-Low Threshold
Power-Low Hysteresis
OUT to GND Pulldown Impedance
MARGIN
Pullup Current
MARGIN
Input Voltage
MARGIN
Glitch Rejection
I
IN
V
IL
V
IH
2.0
100
t
D-GATE
V
OL
V
OUT_
falling
V
OUT_
rising
I
SOURCE
= 0.5µA
During power-up and power-down,
V
GATE_
= 1V
During power-up and power-down,
V
GATE_
= 5V
When disabled, V
GATE_
= 5V, V
IN_
≥
2.7V
When disabled, V
GATE_
= 5V, V
IN_
≥
4V
SET falling, 25mV overdrive
V
IN_
≥
2.7V, I
SINK
= 1mA, output asserted
V
IN_
≥
4.0V, I
SINK
= 4mA, output asserted
Differential between each of the OUT_ and
the ramp voltage during power-up and
power-down, Figure 1 (Note 5)
Differential between each of the OUT_ and
the ramp voltage, Figure 1 (Note 5)
OUT_ falling
OUT_ rising
IN_ > 2.7V (Note 6)
7
75
125
IN_ +
4.2
2.5
2.5
91.5
92.5
0.5
IN_ +
5.0
4
4
9.5
20
10
0.3
0.4
180
IN_ +
5.8
93.5
%
%
V
µA
µA
mA
µs
V
MAX6880–MAX6883
V
TRK
mV
V
TRK_F
V
TH_PL
V
TH_PLHYS
200
125
250
142
10
100
10
310
170
mV
mV
mV
Ω
13
0.8
µA
V
ns
Note 1:
Specifications guaranteed for the stated global conditions. 100% production tested at T
A
= +25°C and T
A
= +85°C.
Specifications at T
A
= -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at
least one of IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V.
Note 2:
A current I
D
= 2.5µA ±15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a refer-
ence for t
DELAY
and t
TIMEOUT
.
Note 3:
The total DELAY is t
DELAY
= 200µs + (500kΩ x C
DELAY
). Leave DELAY unconnected for 200µs delay. The total TIMEOUT is
t
TIMEOUT
= 200µs + (500kΩ x C
TIMEOUT
). Leave TIMEOUT unconnected for 200µs timeout.
Note 4:
A current I
S
= 25µA ±10% is generated internally and used as a reference for t
FAULT
, t
RETRY
, and slew rate.
Note 5:
During power-up, only the condition OUT_ < ramp - V
TRK
is checked in order to stop the ramp. However, both conditions
OUT_ < ramp – V
TRK_F
and OUT_ > ramp + V
TRK_F
cause a fault. During power-down, only the condition OUT > ramp +
V
TRK
is checked in order to stop the ramp. However, both conditions OUT_ < ramp - V
TRK_F
and OUT_ > ramp + V
TRK_F
cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by
more than 2 x V
TRK_F
, a fault condition is asserted.
Note 6:
A 100Ω pulldown to GND activated by a fault condition. See the
Internal Pulldown
section.
_______________________________________________________________________________________
3
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
MAX6880–MAX6883
250mV UP =
FAULT THRESHOLD
250mV UP =
FAULT THRESHOLD
125mV UP =
STOP RAMP THRESHOLD
125mV DOWN =
STOP RAMP THRESHOLD
250mV DOWN =
FAULT THRESHOLD
250mV DOWN =
FAULT THRESHOLD
REFERENCE RAMP
REFERENCE RAMP
POWER-UP
POWER-DOWN
Figure 1. Stop Ramp/Fault Window During Power-Up and Power-Down
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_R
EN/UV
V
EN_F
IN1 = 3.3V
IN2 = 1.8V
IN_
IN3 = 0.7V
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 3.3V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
t
DELAY
t
DELAY
t
DELAY
PG/RST
t
TIMEOUT
Figure 2. Sequencing In Normal Mode
4
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
MAX6880–MAX6883
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_R
EN/UV
IN1 = 3.3V
IN2 = 1.8V
IN_
IN3 = 0.7V
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
OUT_ FORCED
BELOW V
TH_PG
OUT1 = 3.3V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
CAPACITOR-
ADJUSTED
SLEW RATE
t
DELAY
t
DELAY
t
DELAY
PG/RST
t
TIMEOUT
FORCED INTO QUICK SHUTDOWN WHEN OUT1 FALLS BELOW 92.5% of IN1
Figure 3. Sequencing In Fast Shutdown Mode
_______________________________________________________________________________________
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
