1M x 18
2.5V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Flow-Through Outputs
◆
◆
◆
◆
◆
◆
◆
IDT71T75902
Features
1M x 18 memory configuration
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW
1
-
BW
2
control (May tie active)
◆
◆
◆
◆
◆
◆
◆
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram — 1M x 18
LBO
Address A [0:19]
CE
1
, CE
2
CE
2
R/W
CEN
ADV/LD
BWx
Input Register
1M x 18 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
DI
DO
D
Clk
Q
Control Logic
Mux
Clock
Sel
OE
Gate
(optional)
TMS
TDI
TCK
TRST
Data I/O [0:15], I/O P[1:2]
JTAG
TDO
5319 drw 01a
SEPTEMBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC-5319/10
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
The IDT71T75902 is a 2.5V high-speed 18,874,368-bit (18 Megabit)
synchronous SRAM organized as 1M x 18. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
or writes and reads. Thus it has been given the name ZBT
TM
, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle occurs,
be it read or write.
The IDT71T75902 contain address, data-in and control signal regis-
ters. The outputs are flow-through (no output data register). Output enable
is the only asynchronous signal and can be used to disable the outputs
at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71T75902 to be
suspended as long as necessary. All synchronous inputs are
ignored when
CEN
is high and the internal device registers will hold their
previous values.
Description
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75902 has an on-chip burst counter. In the burst mode,
the IDT71T75902 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71T75902 SRAM utilize IDT’s high-performance CMOS
process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
Pin Description Summary
A
0
-A
19
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P2
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
5319 tbl 01a
6.42
2
Pin Definitions
Symbol
A
0
-A
19
ADV/LD
Pin Function
Address Inputs
Advance / Load
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
(1)
Commercial and Industrial Temperature Ranges
I/O
I
I
Activ-
e
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low,
CEN
low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the
chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD
is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place one clock cycle later.
R/W
CEN
Read / Write
Clock Enable
I
I
N/A
LOW Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of
CEN
sampled high on the device outputs
is as if the low to high clock transition did not occur. For normal operation,
CEN
must be sampled low at
rising edge of clock.
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW
2
) must be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle
later.
BW
1
-B
2
can all be tied low if always doing write to the entire 18-bit word.
LOW Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71T75902 (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect
cycle. The ZBT
TM
has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is
initiated.
HIGH Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted
polarity but otherwise identical to
CE
1
and
CE
2
.
N/A
N/A
This is the clock input to the IDT71T75902. Except for
OE,
all timing references for the device are made
with respect to the rising edge of CLK.
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
BW
1
-BW
2
Individual Byte
Write Enables
I
CE
1
,
CE
2
Chip Enables
I
CE
2
CLK
Chip Enable
Clock
I
I
I/O
I
I/O
0
-I/O
31
Data Input/Output
I/O
P1
-I/O
P2
LBO
Linear Burst Order
LOW Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected. When
LBO
is
low the Linear burst sequence is selected.
LBO
is a static input, and it must not change during device
operation.
LOW
Asynchronous output enable.
OE
must be low to read data from the IDT71T75902. When
OE
is HIGH the
I/O pins are in a high-impedance state.
OE
does not need to be actively controlled for read and write
cycles. In normal operation,
OE
can be tied low.
Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
OE
Output Enable
I
TMS
TDI
TCK
TDO
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset
(Optional)
I
I
I
O
N/A
N/A
N/A
N/A
TRST
I
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
LOW reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used
TRST
can be left floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75902 to
HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
N/A
N/A
N/A
2.5V core power supply.
2.5V I/O Supply.
Ground.
5319 tbl 02a
ZZ
V
DD
V
DDQ
V
SS
NOTE:
Sleep Mode
Power Supply
Power Supply
Ground
I
N/A
N/A
N/A
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3,6)
V
TERM
(4,6)
V
TERM
(5,6)
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Ambient
Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Commercial
-0.5 to +3.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
0 to +70
-55 to +125
-55 to +125
2.0
50
Industrial
-0.5 to +3.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
-40 to +85
-55 to +125
-55 to +125
2.0
50
Unit
V
V
V
V
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage — Inputs
Input High Voltage — I/O
Input Low Voltage
Min.
2.375
2.375
0
1.7
1.7
-0.3
(1)
Typ.
2.5
2.5
0
____
____
____
Max.
2.625
2.625
0
V
DD
+0.3
V
DDQ
+0.3
(2)
0.7
Unit
V
V
V
V
V
V
5319 tbl 03
T
A
(7)
T
BIAS
T
STG
P
T
I
OUT
o
C
C
C
o
o
W
mA
5319 tbl 06
NOTE:
1. V
IL
(min.) = –0.8V for pulse width less than t
CYC
/2, once per cycle.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
7. During production testing, the case temperature equals T
A
.
Recommended Operating
Temperature and Supply Voltage
Grade
Commerical
Industrial
Ambient
Temperature
(1)
0 °C to +70 °C
-40 °C to +85 °C
V
SS
OV
OV
V
DD
2.5V ± 5%
2.5V ± 5%
V
DDQ
2.5V ± 5%
2.5V ± 5%
5319 tbl 05
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
TQFP Capacitance
(T
A
= +25°C, f = 1.0MHz)
°
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
5319 tbl 07
BGA Capacitance
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
(T
A
= +25°C, f = 1.0MHz)
°
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5319 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 1M x 18, 100 TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DDQ
V
SS
NC
NC
I/O
8
I/O
9
V
SS
V
DDQ
I/O
10
I/O
11
V
SS
(1)
V
DD
V
DD
(2)
V
SS
I/O
12
I/O
13
V
DDQ
V
SS
I/O
14
I/O
15
I/O
P2
NC
V
SS
V
DDQ
NC
NC
NC
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/L
D
A
19
A
18
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
71T75902
PKG100
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
NC
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
SS
(1)
V
DD
ZZ
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
5319 drw 02a
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to V
SS
as long as the input voltage is < V
IL
.
2. Pin 16 does not have to be connected directly to V
DD
as long as the input voltage is > V
IH
.
3. Pins 38, 39 and 43 will be pulled internally to V
DD
if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39
and 43 could be tied to V
DD
or V
SS
and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins38, 39 and 43 could be left unconnected “NC” and the JTAG
circuit will remain disabled from power up.
NC/TMS
(3)
NC/TDI
(3)
V
SS
V
DD
NC/TDO
(3)
NC/TCK
(3,4)
A
11
A
12
A
13
A
14
A
15
A
16
A
17
LBO
A
5
A
4
A
3
A
2
A
1
A
0
6.42
5
FPGA/CPLD
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