19-1016; Rev 2; 2/96
CMOS, Quad, Serial-Interface
8-Bit DAC
_______________General Description
The MAX500 is a quad, 8-bit, voltage-output digital-to-
analog converter (DAC) with a cascadable serial inter-
face. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cas-
cading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
____________________________Features
o
Buffered Voltage Outputs
o
Double-Buffered Digital Inputs
o
Microprocessor and TTL/CMOS Compatible
o
Requires No External Adjustments
o
Two- or Three-Wire Cascadable Serial Interface
o
16-Pin DIP/SO Package and 20-Pin LCC
o
Operates from Single or Dual Supplies
MAX500
______________Ordering Information
TEMP. RANGE PIN-PACKAGE ERROR (LSB)
PART
MAX500ACPE
0°C to +70°C
16 Plastic DIP
±1
MAX500BCPE
MAX500ACWE
MAX500BCWE
MAX500BC/D
MAX500AEPE
MAX500BEPE
MAX500AEWE
MAX500BEWE
MAX500AEJE
MAX500BEJE
MAX500AMJE
MAX500BMJE
MAX500AMLP
MAX500BMLP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
16 Plastic DIP
16 Wide SO
16 Wide SO
Dice*
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
16 CERDIP
16 CERDIP
16 CERDIP
16 CERDIP
20 LCC
20 LCC
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
±1
±2
±1
±2
________________________Applications
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
________________Functional Diagram
SRO
V
REF
C
AGND
DGND V
SS
V
DD
LDAC V
REF
A/B V
REF
D
V
OUT
A
INPUT
REG A
DAC
REG A
DAC A
*Contact factory for dice specifications.
_________________Pin Configurations
V
OUT
B
TOP VIEW
V
OUT
B
1
16
V
OUT
C
15
V
OUT
D
14
V
DD
DATA BUS
10/11-
BIT
SHIFT
REGISTER
INPUT
REG B
DAC
REG B
DAC B
V
OUT
C
INPUT
REG C
DAC
REG C
DAC C
V
OUT
A
2
V
SS
3
V
REF
A/B
4
MAX500
13
V
REF
C
12
V
REF
D
11
SRO
10
SCL
9
LOAD
V
OUT
D
INPUT
REG D
CONTROL
LOGIC
DAC
REG D
DAC D
AGND
5
DGND
6
LDAC
7
MAX500
SDA
8
LOAD SDA
SCL
DIP/SO
Pin Configurations continued on last page.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS, Quad, Serial-Interface
8-Bit DAC
MAX500
ABSOLUTE MAXIMUM RATINGS
Power Requirements
V
DD
to AGND...........................................................-0.3V, +17V
V
DD
to DGND ..........................................................-0.3V, +17V
V
SS
to DGND ..................................................-7V, (V
DD
+ 0.3V)
V
DD
to V
SS
...............................................................-0.3V, +24V
Digital Input Voltage to DGND ....................-0.3V, (V
DD
+ 0.3V)
V
REF
to AGND .............................................-0.3V, (V
DD
+ 0.3V)
V
OUT
to AGND (Note 1)...............................-0.3V, (V
DD
+ 0.3V)
Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C) ...............800mW
LCC (derate 9.09mW/°C above +70°C).......................727mW
Operating Temperature Ranges
MAX500_C_ _ ....................................................0°C to + 70°C
MAX500_E_ _...................................................-40°C to +85°C
MAX500_M_ _ ................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1:
The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded.
Typical short-circuit current to AGND is 25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Dual Supplies
(V
DD
= +11.4V to +16.5V, V
SS
= -5V ±10%, AGND = DGND = 0V, V
REF
= +2V to (V
DD
- 4V), T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Tempco
V
DD
= 15V ±5%,
V
REF
= 10V
MAX500A
MAX500B
Guaranteed monotonic
MAX500A
MAX500B
V
REF
= 10V
T
A
= +25°C
Zero-Code Error
T
A
= T
MIN
to T
MAX
Zero-Code Tempco
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
Reference Input Capacitance
Channel-to-Channel Isolation
AC Feedthrough
DIGITAL INPUTS
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage Current
Digital Input Capacitance
2
V
IH
V
IL
V
OH
V
OL
I
OUT
= -1mA, SRO only
I
OUT
= 1mA, SRO only
(Note 4)
T
A
= +25°C (Note 2)
Excluding
LOAD
LOAD
= 0V
V
DD
- 1
0.4
±1
30
8
V
REF
C, V
REF
D
V
REF
A/B
T
A
= +25°C, code dependent (Note 2)
T
A
= +25°C (Notes 2, 3)
T
A
= +25°C (Notes 2, 3)
2
11
5.5
-60
-70
2.4
5.5
0.8
MAX500A
MAX500B
MAX500A
MAX500B
±30
V
DD
- 4
MAX500A
MAX500B
8
±1
±2
±1/2
±1
±1
±1/2
±1
±5
±15
±20
±20
±30
Bits
LSB
LSB
LSB
LSB
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mV
µV/°C
V
kΩ
100
pF
dB
dB
V
V
V
V
µA
pF
_______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V
DD
= +11.4V to +16.5V, V
SS
= -5V ±10%, AGND = DGND = 0V, V
REF
= +2V to (V
DD
- 4V), T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
V
OUT
Settling Time
Digital Feedthrough
Digital Crosstalk
Output Load Resistance
Positive
SUPPLIES
POWER
Supply Voltage
Positive Supply Voltage
Positive Supply Current
V
DD
V
DD
I
DD
I
SS
TA = +25°C (Note 2)
To ±1/2LSB, V
REF
= 10V, V
DD
= +15V,
2kΩ in parallel with 100pF load (Note 2)
(Note 5)
(Note 5)
V
OUT
= 10V
For specified performance
For specified performance
Outputs unloaded
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
150
150
0
350
350
(Note 7)
(Note 7)
t
LDW
t
LDS
t
LDAC
t
D1
t
1
t
H
t
1
t
2
(Note 7)
(Note 7)
t
LDAC
t
S1
t
S2
t
S3
t
D1
C
LOAD
= 50pF
Start condition
Stop condition
150
150
100
125
150
C
LOAD
= 50pF
350
0
350
350
50
50
150
150
150
150
50
50
2
11.4
11.4
16.5
16.5
10
12
-9
-10
3
8
2.5
50
50
4.5
V/µs
µs
nV-s
nV-s
kΩ
V
V
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX500
Negative Supply Current
Outputs unloaded
mA
SWITCHING CHARACTERISTICS
(T
A
= +25°C, Note 6)
3-Wire Mode
SCL Setup
SDA Valid to
SDA Valid to SCL Setup
SDA Valid to SCL Hold
SCL High Time
SCL Low Time
SCL Rise Time
SCL Fall Time
LOAD
Pulse Width
LOAD
Delay from SCL
LDAC
Pulse Width
SRO Output Delay
2-Wire Mode
SCL High Time
SDA Valid to SCL Hold
SCL High Time
SCL Low Time
SCL Rise Time
SCL Fall Time
LDAC
Pulse Width
SCL Valid to SDA Setup
SDA Valid to SCL Setup
SDA Valid to Rising SCL
SRO Output Delay
t
S1
t
S1
t
H
t
1
t
2
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
_______________________________________________________________________________________
3
CMOS, Quad, Serial-Interface
8-Bit DAC
MAX500
ELECTRICAL CHARACTERISTICS—Single Supply
(V
DD
= +15V ±5%, V
SS
= AGND = DGND = 0V, V
REF
= 10V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Tempco
V
REF
= 10V
T
A
= +25°C
Zero-Code Error
T
A
= T
MIN
to T
MAX
MAX500A
MAX500B
MAX500A
MAX500B
±30
Guaranteed monotonic
MAX500A
MAX500B
±5
±15
±20
±20
±30
SYMBOL
CONDITIONS
MIN
8
V
DD
= 15V ±5%,
V
REF
= 10V
MAX500A
MAX500B
MAX500A
MAX500B
±1
±2
±1/2
±1
±1
±1/2
±1
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
ppm/°C
mV
Zero-Code Tempco
REFERENCE INPUT—All
specifications are the same as for dual supplies.
DIGITAL INPUTS—All
specifications are the same as for dual supplies.
DYNAMIC PERFORMANCE—All
specifications are the same as for dual supplies.
POWER SUPPLIES
Positive Supply Voltage
V
DD
For specified performance
T
A
= +25°C
Positive Supply Current
I
DD
Outputs unloaded
T
A
= T
MIN
to T
MAX
SWITCHING CHARACTERISTICS—All
specifications are the same as for dual supplies.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
µV/°C
14.25
15.75
10
12
V
mA
Guaranteed by design. Not production tested.
T
A
= +25°C, V
REF
= 10kHz, 10V peak-to-peak sine wave.
LOAD
has a weak internal pull-up resistor to V
DD
.
DAC switched from all 1s to all 0s, and all 0s to all 1s code.
Sample tested at +25°C to ensure compliance.
Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given
because the other digital inputs should be stable when SCL transitions.
__________________________________________Typical Operating Characteristics
RELATIVE ACCURACY vs. REFERENCE VOLTAGE
MAX500-04
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY (LSB)
T
A
= +25°C, V
SS
= -5V
0.5
MAX500-05
1.0
T
A
= +25°C, V
SS
= -5V
RELATIVE ACCURACY (LSB)
0.5
1.0
V
DD
= 15V
0
0
-0.5
V
DD
= 12V
-0.5
V
DD
= 12V
V
DD
= 15V
0
2
4
6
V
REF
(V)
8
10
12
14
-1.0
0
2
4
6
V
REF
(V)
8
10
12
14
-1.0
4
_______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
____________________________Typical Operating Characteristics (continued)
MAX500
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
MAX500-01
SUPPLY CURRENT
vs. TEMPERATURE
MAX500-02
ZERO-CODE ERROR
vs. TEMPERATURE
1.5
ZERO-CODE ERROR (mV)
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
V
SS
= -5V
-55
-25
0
25
50
75
100
125
V
OUT
D
V
OUT
B
V
OUT
A
MAX500-03
16
V
SS
= -5V
14
12
I
SINK
(mA)
10
8
6
4
2
0
0
2
4
6
8
R
O
≅
200Ω
V
SS
= 0V
12
10
SUPPLY CURRENT (mA)
8
6
4
2
0
-2
-4
-6
I
SS
I
DD
2.0
V
OUT
C
10
-55
-25
0
25
50
75
100
125
V
OUT
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________Detailed Description
The MAX500 has four matched voltage-output digital-to-
analog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
R
…
2R
2R
DB0
V
REF
DB0
AGND
DB5
2R
R
R
V
OUT
of the V
REF
inputs is code dependent. The lowest
value, approximately 11kΩ (5.5kΩ for V
REF
A/B), occurs
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at V
REF
is code depen-
dent, the DAC’s reference sources should have an out-
put impedance of no more than 20Ω (no more than
10Ω for V
REF
A/B). The input capacitance at V
REF
is
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for V
REF
A/B). V
OUT
A, V
OUT
B,
V
OUT
C, and V
OUT
D can be represented by a digitally
programmable voltage source as:
V
OUT
= N
b
x V
REF
/ 256
where N
b
is the numeric value of the DAC’s binary
input code.
2R
2R
Output Buffer Amplifiers
All voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/µs.
When driving 2kΩ in parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4µs. The buffers will also drive
2kΩ in parallel with 500pF to 10V levels without oscilla-
tion. Typical dynamic response and settling perfor-
mance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The out-
put circuitry incorporates a pull-down circuit to actively
drive V
OUT
to within +15mV of the negative supply
(V
SS
). The buffer circuitry allows each DAC output to
5
DB5
DB6
DB6
DB7
DB7
…
…
Figure 1. Simplified DAC Circuit Diagram
V
REF
Input
The voltage at the V
REF
pins (pins 4, 12, and 13) sets
the full-scale output of the DAC. The input impedance
_______________________________________________________________________________________
能源基础设施
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
