74AUP1G74
Rev. 11 — 3 July 2017
Low-power D-type flip-flop with set and reset; positive-
edge trigger
Product data sheet
1
General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered
D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must
be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable
operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
2
Features and benefits
•
Wide supply voltage range from 0.8 V to 3.6 V
•
High noise immunity
•
Complies with JEDEC standards:
–
JESD8-12 (0.8 V to 1.3 V)
–
JESD8-11 (0.9 V to 1.65 V)
–
JESD8-7 (1.2 V to 1.95 V)
–
JESD8-5 (1.8 V to 2.7 V)
–
JESD8-B (2.7 V to 3.6 V)
•
ESD protection:
–
HBM JESD22-A114F Class 3A exceeds 5000 V
–
MM JESD22-A115-A exceeds 200 V
–
CDM JESD22-C101E exceeds 1000 V
•
Low static power consumption; I
CC
= 0.9 μA (maximum)
•
Latch-up performance exceeds 100 mA per JESD 78 Class II
•
Inputs accept voltages up to 3.6 V
•
Low noise overshoot and undershoot < 10 % of V
CC
•
I
OFF
circuitry provides partial power-down mode operation
•
Multiple package options
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74
3
Ordering information
Package
Temperature range
Name
VSSOP8
XSON8
XSON8
XQFN8
XSON8
XSON8
X2SON8
Table 1. Ordering information
Type number
74AUP1G74DC
74AUP1G74GT
74AUP1G74GF
74AUP1G74GM
74AUP1G74GN
74AUP1G74GS
74AUP1G74GX
Description
Version
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 × 1.6 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1.0 × 0.35 mm
plastic thermal enhanced extremely thin
small outline package; no leads; 8 terminals;
body 1.35 × 0.8 × 0.35 mm
SOT1089
SOT902-2
SOT1116
SOT1203
SOT1233
4
Marking
Marking code
p74
p74
54
p74
54
54
54
[1]
Table 2. Marking codes
Type number
74AUP1G74DC
74AUP1G74GT
74AUP1G74GF
74AUP1G74GM
74AUP1G74GN
74AUP1G74GS
74AUP1G74GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 11 — 3 July 2017
2 / 29
Nexperia
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74
5
Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah725
Q
Q
S
Q
C1
1D
R
001aah726
Figure 1. Logic symbol
C
Figure 2. IEC logic symbol
Q
C
C
D
C
C
Q
C
RD
SD
CP
001aae087
C
C
Figure 3. Logic diagram
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 11 — 3 July 2017
3 / 29
Nexperia
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74
6
Pinning information
6.1 Pinning
74AUP1G74
CP
1
8
V
CC
D
2
7
SD
74AUP1G74
CP
D
Q
GND
1
2
3
4
001aae322
Q
3
6
RD
8
7
6
5
V
CC
SD
RD
Q
GND
4
5
Q
001aae323
Transparent top view
Figure 4. Pin configuration SOT765-1
Figure 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP1G74
terminal 1
index area
SD
1
V
CC
7
CP
74AUP1G74
CP 1
7
8
V
CC
D
2
4
GND
Q
3
5
aaa-027030
8
SD
RD
2
6
D
6
RD
4
Q
3
5
Q
GND
Q
001aae324
Transparent top view
Transparent top view
Figure 6. Pin configuration SOT902-2
Figure 7. Pin configuration SOT1233
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 11 — 3 July 2017
4 / 29
Nexperia
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74
6.2 Pin description
Table 3. Pin description
Symbol Pin
SOT765-1, SOT833-1, SOT1089, SOT1116,
SOT1203 and SOT1233
CP
D
Q
GND
Q
RD
SD
V
CC
1
2
3
4
5
6
7
8
Description
SOT902-2
7
6
5
4
3
2
1
8
clock input
data input
complement output
ground (0 V)
true output
asynchronous reset input (active LOW)
asynchronous set input (active LOW)
supply voltage
7
Functional description
[1]
Table 4. Function table for asynchronous operation
Input
SD
L
H
L
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
[1]
Table 5. Function table for synchronous operation
Input
SD
H
H
[1]
Output
RD
H
H
CP
↑
↑
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
74AUP1G74
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 11 — 3 July 2017
5 / 29
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