62.5MHz to 250MHz, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
Data Sheet
86004-01
G
ENERAL
D
ESCRIPTION
The 86004-01 is a high performance 1-to-4 LVCMOS/LVTTL
Clock Buffer and a member of the family of High Performance
Clock Solutions from IDT. The 86004-01 has a fully integrated
PLL and can be configured as zero delay buffer and has an input
and output frequency range of 62.5MHz to 250MHz. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output divider.
F
EATURES
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 62.5MHz to 250MHz
• Input frequency range: 62.5MHz to 250MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)
• Output skew: 60ps (maximum)
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 5V tolerant input
• -40°C to 70°C ambient operating temperature
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
F_SEL
0
1
Input/Output
Frequency Range (MHz)
Minimum
125
62.5
Maximum
250
125
• Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
86004-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision D January 21, 2016
86004-01 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 3,
13, 15
2, 7, 14
4
5
6
8
9
10
11
12, 16
Name
Q1, Q0,
Q3, Q2
GND
F_SEL
V
DD
CLK
V
DDA
PLL_SEL
FB_IN
MR
V
DDO
Type
Output
Power
Input
Power
Input
Power
Input
Input
Input
Power
Pulldown
Description
Clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels.
Power supply ground.
Frequency range select input. When LOW, I/O frequency range is from
125MHz to 250Mz. When HIGH, I/O frequency range is from
62.5MHz to 125MHz. LVCMOS/LVTTL interface levels.
Core supply pin.
Pulldown LVCMOS/LVTTL clock input.
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with “zero delay”.
Pulldown
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
Output supply pins.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DD
, V
DDO
= 3.465V
V
DD
, V
DDO
= 2.625V
3.3V ± 5%
5
7
Test Conditions
Minimum
Typical
4
51
51
23
17
12
Maximum
Units
pF
kΩ
kΩ
pF
pF
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
F_SEL
0
1
Input/Output
Frequency Range (MHz)
Minimum
125
62.5
Maximum
250
125
©2016 Integrated Device Technology, Inc
2
Revision D January 21, 2016
86004-01 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to +5.0V
-0.5V to V
DDO
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
100
16
6
Units
V
V
V
mA
mA
mA
NOTE: Special thermal handling maybe required in some configurations.
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
100
16
6
Units
V
V
V
mA
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
96
15
6
Units
V
V
V
mA
mA
mA
NOTE: Special thermal handling maybe required in some configurations.
©2016 Integrated Device Technology, Inc
3
Revision D January 21, 2016
86004-01 Data Sheet
T
ABLE
4D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK, MR,
FB_IN, F_SEL
PLL_SEL
CLK, MR,
FB_IN, F_SEL
PLL_SEL
V
OH
Output High Voltage; NOTE 1
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDO
= 3.465V
V
DDO
= 2.625V
-5
-150
2.6
1.8
0.5
Minimum
2.0
1.7
-0.3
-0.3
Typical
Maximum
5.0
5.0
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
Input High Current
I
IL
Input Low Current
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 3.465V or 2.625V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
70°C
Symbol
f
MAX
tp
LH
t(Ø)
tsk(o)
tjit(cc)
t
L
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
F_SEL = 0
300
44
50
Test Conditions
F_SEL = 0
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
PLL_SEL = 0V
F_SEL = 0
F_SEL = 1
Minimum
125
62.5
4.1
-75
5.1
50
Typical
Maximum
250
125
6.1
175
60
65
45
1
750
56
Units
MHz
MHz
ns
ps
ps
ps
ps
mS
ps
%
F_SEL = 1
47
50
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.All parameters measured at f
MAX
unless
noted otherwise.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
4
Revision D January 21, 2016
86004-01 Data Sheet
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
70°C
Symbol
f
MAX
tp
LH
t(Ø)
tsk(o)
tjit(cc)
t
L
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
300
Test Conditions
F_SEL = 0
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
PLL_SEL = 0V
F_SEL = 0
F_SEL = 1
Minimum
125
62.5
4.25
-300
5.25
Typical
Maximum
250
125
6.25
0
60
65
45
1
700
Units
MHz
MHz
ns
ps
ps
ps
ps
mS
ps
odc
Output Duty Cycle
45
50
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.All parameters measured at f
MAX
unless
noted otherwise.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
70°C
Symbol
f
MAX
tp
LH
t(Ø)
tsk(o)
tjit(cc)
t
L
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
300
Test Conditions
F_SEL = 0
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
PLL_SEL = 0V
F_SEL = 0
F_SEL = 1
Minimum
125
62.5
4.5
-100
5.5
Typical
Maximum
250
125
6.5
250
55
65
45
1
700
Units
MHz
MHz
ns
ps
ps
ps
ps
mS
ps
odc
Output Duty Cycle
45
50
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.All parameters measured at f
MAX
unless
noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
5
Revision D January 21, 2016
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