MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
February 1984
Revised May 2005
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT373
octal
D-type
latches
and
MM74HCT374 Octal D-type flip flops advanced silicon-gate
CMOS technology, which provides the inherent benefits of
low power consumption and wide power supply range, but
are LS-TTL input and output characteristic & pin-out com-
patible. The 3-STATE outputs are capable of driving 15 LS-
TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to V
CC
and ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CON-
TROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
TTL input characteristic compatible
s
Typical propagation delay: 20 ns
s
Low input current: 1
P
A maximum
s
Low quiescent current: 80
P
A maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
MM74HCT373WM
MM74HCT373SJ
MM74HCT373MTC
MM74HCT373N
MM74HCT374WM
MM74HCT374SJ
MM74HCT374MTC
MM74HCT374N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Descriptions
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS005367
www.fairchildsemi.com
MM74HCT373 • MM74HCT374
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
0.5 to
7.0V
1.5 to V
CC
1.5V
0.5 to V
CC
0.5V
r
20 mA
r
35 mA
r
70 mA
65
q
C to
150
q
C
Max
5.5
V
CC
Units
V
V
4.5
0
40
85
q
C
DC Electrical Characteristics
V
CC
5V
r
10% (unless otherwise specified)
Parameter
Minimum HIGH Level
Input Voltage
V
IL
V
OH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
V
OL
Maximum LOW Level
Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
I
IN
I
OZ
Maximum Input
Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
I
OUT
V
IN
V
CC
or GND
0
P
A
2.4V or 0.5V (Note 4)
8.0
1.0
80
1.3
160
1.5
V
IN
V
OUT
Enable
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
CC
or GND,
V
CC
or GND
V
IH
or VIL
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
4.5V
5.5V
V
CC
4.2
5.7
V
CC
0.1
3.98
4.98
V
CC
0.1
3.84
4.84
V
CC
0.1
3.7
4.7
V
V
V
Conditions
T
A
Typ
2.0
0.8
25
q
C
T
A
Symbol
V
IH
40 to 85
q
C
T
A
55 to 125
q
C
Guaranteed Limits
2.0
0.8
2.0
0.8
Units
V
V
V
IH
or V
IL
r
0.1
r
1.0
r
1.0
P
A
r
0.5
r
5.0
r
10
P
A
P
A
mA
Note 4:
Measured per pin. All others tied to V
CC
or ground.
www.fairchildsemi.com
4
MM74HCT373 • MM74HCT374
AC Electrical Characteristics
MM74HCT373: V
CC
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
W
t
S
t
H
5.0V, t
r
t
f
6 ns T
A
25
q
C (unless otherwise specified)
Conditions
C
L
C
L
C
L
R
L
C
L
R
L
45 pF
45 pF
45 pF
1 k
:
5 pF
1 k
:
Typ
18
21
20
18
Guaranteed
Limit
25
30
28
25
16
5
10
Units
ns
ns
ns
ns
ns
ns
ns
Parameter
Maximum Propagation Delay
Data to Output
Maximum Propagation Delay
Latch Enable to Output
Maximum Enable Propagation Delay
Control to Output
Maximum Disable Propagation Delay
Control to Output
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
AC Electrical Characteristics
MM74HCT373: V
CC
Symbol
5.0V
r
10%, t
r
Parameter
t
f
6 ns (unless otherwise specified)
Conditions
C
L
C
L
C
L
C
L
C
L
C
L
R
L
C
L
R
L
C
L
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
:
50 pF
1 k
:
50 pF
8
12
16
5
10
10
20
OC
OC
V
CC
GND
5
52
C
PD
V
CC
2 f
I
CC
V
CC
, and the no load dynamic current consumption,
T
A
25
q
C
Typ
22
30
25
32
21
30
21
30
40
35
45
30
40
30
T
A
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
37
50
44
56
37
50
37
15
20
6
13
10
20
45
60
53
68
45
60
45
18
24
8
20
10
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
pF
t
PHL
, t
PLH
Maximum Propagation
Delay Data to Output
t
PHL
, t
PLH
Maximum Propagation Delay
Latch Enable to Output
t
PZH
, t
PZL
Maximum Enable Propagation
Delay Control to Output
t
PHZ
, t
PLZ
Maximum Disable Propagation
Delay Control to Output
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
t
W
t
S
t
H
C
IN
C
OUT
C
PD
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 5)
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
I
S
C
PD
V
CC
f
I
CC
.
5
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