74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
January 2008
74AC573, 74ACT573
Octal Latch with 3-STATE Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Inputs and outputs on opposite sides of package
■
■
■
■
■
General Description
The 74AC573 and 74ACT573 are high-speed octal
latches with buffered common Latch Enable (LE) and
buffered common Output Enable (OE) inputs.
The 74AC573 and 74ACT573 are functionally identical
to the 74AC373 and 74ACT373 but with inputs and
outputs on opposite sides.
allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to 74AC373 and 74ACT373
3-STATE outputs for bus interfacing
Outputs source/sink 24mA
74ACT573 has TTL-compatible inputs
Ordering Information
Order Number
74AC573SC
74AC573SJ
74AC573MTC
74ACT573SC
74ACT573SJ
74ACT573MTC
74ACT573PC
Package
Number
M20B
M20D
MTC20
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
www.fairchildsemi.com
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Functional Description
The 74AC573 and 74ACT573 contain eight D-type
latches with 3-STATE output buffers. When the Latch
Enable (LE) input is HIGH, data on the D
n
inputs enters
the latches. In this condition the latches are transparent,
i.e., a latch output will change state each time its D-type
input changes. When LE is LOW the latches store the
information that was present on the D-type inputs a
setup time preceding the HIGH-to-LOW transition of LE.
The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
Inputs
OE
L
L
L
H
Outputs
D
H
L
X
X
LE
H
H
L
X
O
n
H
L
O
0
Z
H
=
HIGH Voltage
L
=
LOW Voltage
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of
Latch Enable
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
www.fairchildsemi.com
2
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
www.fairchildsemi.com
3
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
www.fairchildsemi.com
4
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
DC Electrical Characteristics for AC
T
A
=
+25°C
Symbol
V
IH
T
A
=
–40°C to +85°C
Units
V
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
–75
µA
mA
mA
µA
µA
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
Guaranteed Limits
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IL
or V
IH
,
I
OH
=
–12mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(1)
0.002
0.001
0.001
V
IN
=
V
IL
or V
IH
,
I
OL
=
12mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
;
V
I
=
V
CC
, GND;
V
O
=
V
CC
, GND
I
OUT
=
50µA
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
I
IN(2)
I
OLD
I
OHD
I
CC(2)
I
OZ
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(3)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
5.5
5.5
5.5
5.5
5.5
4.0
±0.25
40.0
±2.5
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
www.fairchildsemi.com
5
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