GTL2009
3-bit GTL Front-Side Bus frequency comparator
Rev. 01 — 22 September 2005
Product data sheet
1. General description
The GTL2009 is designed for the Nocona and Dempsey/Blackford dual Intel Xeon
processor platforms to compare the Front-Side Bus (FSB) frequency settings and set the
common FSB frequency at the lowest setting if both processor slots are occupied or the
FSB setting of the occupied processor slot if only one processor is being used. A default
FSB frequency of 100 MHz is initially set upon power-up when V
DD
is greater than 1.5 V.
Magnitude comparisons and frequency multiplexing to compute the common FSB
frequency occurs when the two 3-bit FSB GTL inputs from the chip sets are valid. The
common FSB frequency GTL outputs switch from the default frequency to the computed
frequency when the GTL reference voltage input (VREF) crosses a static 0.6 V internally
generated input comparator reference voltage. The GTL2009 then continually monitors
the FSB frequency and slot occupied inputs for any further changes.
The Nocona and Dempsey/Blackford Xeon processors specify a V
TT
of 1.2 V and 1.1 V,
as well as a nominal V
ref
of 0.76 V and 0.73 V respectively. To allow for future voltage level
changes that may extend V
ref
to 0.63 of V
TT
(minimum of 0.693 V with V
TT
of 1.1 V) the
GTL2009 allows a minimum V
ref
of 0.66 V. Characterization results show that there is little
DC or AC performance variation between these levels.
The GTL2009 is a companion chip to the GTL2006 platform health management
GTL-to-LVTTL translator and the newer GTL2007 that adds an enable function that
disables the error output to the monitoring agent for platforms that monitor the individual
error conditions from each processor.
2. Features
s
Compares FSB frequency inputs to set the lowest frequency as the common bus
frequency.
s
Operates at a range of GTL signal levels
s
3.0 V to 3.6 V operation
s
LVTTL I/O are not 5 V tolerant
s
Companion chip to GTL2006 and GTL2007
s
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
s
Latch-up testing is done to JEDEC Standard JESD78, which exceeds 500 mA
s
Available in TSSOP16 package
Philips Semiconductors
GTL2009
3-bit GTL Front-Side Bus frequency comparator
3. Quick reference data
Table 1:
Quick reference data
T
amb
= 25
°
C
Symbol
t
PLH
t
PHL
Parameter
Conditions
Min
3.0
2.3
Typ
16.5
16.2
Max
30
30
Unit
ns
ns
LOW-to-HIGH propagation delay; C
L
= 30 pF;
BI to BO
V
DD
= 3.3 V
HIGH-to-LOW propagation delay;
BI to BO
4. Ordering information
Table 2:
Ordering information
Package
Name
TSSOP16
Description
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT403-1
Type number Topside
mark
GTL2009PW
GTL2009
5. Functional diagram
GTL2009
VREF
START-UP
A
≥
B
1=B
A
MUX
B
common
FSB
BSEL1
BSEL2
BSEL3
default output is
101 = 100 MHz
V
DD
BO1
BO2
BO3
1BI1
1BI2
1BI3
1AI
2AI
2BI1
2BI2
2BI3
A - BSEL1
A - BSEL2
A - BSEL3
A - Occupied#
B - Occupied#
B - BSEL1
B - BSEL2
B - BSEL3
GTL to TTL
active LOW
A
COMPARE
active LOW
B
A
≥
B
AO2
equal
AO1
GTL to TTL
V
SS
002aaa997
If B - Occupied only, then A
≥
B = 1.
If A - Occupied only, then A
≥
B = 0.
If A and B - Occupied, then A
≥
B = 1 if A frequency higher than B frequency.
Pin assignment: A = LVTTL, B = GTL, I = Input, O = Output.
Refer to
Section 7.2 “Default conditions input”.
Fig 1. Functional diagram of GTL2009
9397 750 13556
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 22 September 2005
2 of 17
Philips Semiconductors
GTL2009
3-bit GTL Front-Side Bus frequency comparator
6. Pinning information
6.1 Pinning
V
DD
VREF
BO3
BO2
BO1
AO2
AO1
V
SS
1
2
3
4
5
6
7
8
002aaa996
16 1BI1
15 1BI2
14 1BI3
13 1AI
12 2AI
11 2BI1
10 2BI2
9
2BI3
GTL2009PW
Fig 2. Pin configuration for TSSOP16
6.2 Pin description
Table 3:
Symbol
V
DD
VREF
BO3
BO2
BO1
AO2
AO1
V
SS
2BI3
2BI2
2BI1
2AI
1AI
1BI3
1BI2
1BI1
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
supply
V
ref
GTL output
GTL output
GTL output
LVTTL output
LVTTL output
ground
GTL input
GTL input
GTL input
LVTTL input
LVTTL input
GTL input
GTL input
GTL input
Description
supply voltage
V
ref
input voltage
BSEL3
BSEL2
BSEL1
A
≥
B
equal
ground supply
B-BSEL3
B-BSEL2
B-BSEL1
B-occupied
A-occupied
A-BSEL3
A-BSEL2
A-BSEL1
9397 750 13556
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 22 September 2005
3 of 17
Philips Semiconductors
GTL2009
3-bit GTL Front-Side Bus frequency comparator
7. Functional description
Refer to
Figure 1 “Functional diagram of GTL2009”.
7.1 Function tables
Table 4:
BSEL3
H
L
L
L
L
H
H
H
FSB frequency selection
BSEL2
L
L
H
H
L
L
H
H
BSEL1
H
H
H
L
L
L
L
H
FSB
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
333 MHz
400 MHz
reserved
Table 5:
FSB frequency comparison
Default on start-up is 101
Processor A FSB
A
≥
B
A<B
not occupied
A
A=B
Table 6:
Processor B FSB
A
≥
B
A<B
B
not occupied
A=B
FSB the same output
Processor B FSB
A>B
A<B
A=B
Compare
A frequency = B frequency
A>B
A<B
A=B
Table 7:
Pin 1AI
A-occupied
L
H
L
H
yes
no
yes
no
no
no
yes
L
L
H
Pin AO1
Pins BO1/BO2/BO3
Common FSB frequency
B
A
B
A
A or B
Processor A FSB
FSB processor A greater than or equal to processor B output
Pin 2AI
B-occupied
L
L
H
H
yes
yes
no
no
Compare
A frequency > B frequency
no
yes
X
X
X
L
H
H
L
H
Pin AO2
9397 750 13556
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 22 September 2005
4 of 17
Philips Semiconductors
GTL2009
3-bit GTL Front-Side Bus frequency comparator
7.2 Default conditions input
The FSB GTL output data is masked and a specific default value (100 MHz) is inserted
upon power-up when V
DD
is greater than 1.5 V. The FSB GTL output data is unmasked
and valid data is supplied when the VREF input crosses a static 0.6 V internally generated
input comparator reference voltage. For slowly rising GTL V
TT
supply (0.7 V/500
µs),
the
switch-over happens at the 0.6 V threshold. For fast rising GTL V
TT
supply (0.7 V/100 ns),
the switch-over typically occurs between 350 ns to 1.5
µs
after the 0.6 V threshold is
exceeded.
The AO1 and AO2 outputs do not have ‘default conditions’ like those assigned to the GTL
outputs. Instead, these two pins will power-up according to the conditions applied to the
1A1 and 2A1 input pins as shown in
Table 8.
If the slot is occupied, the input is LOW.
Table 8:
AO1 and AO2 power-up conditions
H = HIGH; L = LOW.
1AI
L
L
L
L
H
H
H
H
2AI
L
L
H
H
L
L
H
H
V
DD
<1.5 V
>1.5 V
<1.5 V
>1.5 V
<1.5 V
>1.5 V
<1.5 V
>1.5 V
AO1
L
H
L
L
L
L
L
H
AO2
L
H
L
L
L
H
L
H
It is important to note that the AO1 and AO2 outputs may be valid a little before 1.5 V and
will rise with V
DD
. Valid outputs from the system level perspective will be achieved after
V
DD
is in regulation, V
TT
ramps up, and after the internal propagation delay of the
GTL2009. No firm answer for this can be given since the time it takes for V
DD
to be in
regulation varies from 100 ms to 1000 ms, and the rise time of V
TT
is unknown. The
GTL2009 outputs are valid after the GTL inputs are valid plus 19.6 ns (worst-case
propagation delay of the GTL-to-LVTTL path).
9397 750 13556
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 22 September 2005
5 of 17
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