NB2309A
3.3 V Zero Delay
Clock Buffer
The NB2309A is a versatile, 3.3 V zero delay buffer designed to
distribute high-
-speed clocks. It accepts one reference input and drives
out nine low-
-skew clocks. It is available in a 16 pin package.
The -
-1H version of the NB2309A operates at up to 133 MHz, and
has higher drive than the - devices. All parts have on-
-1
-chip PLL’s that
lock to an input clock on the REF pin. The PLL feedback is on-
-chip
and is obtained from the CLKOUT pad.
The NB2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three-
-stated. The select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2309A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle- -cycle jitter. The input
-to-
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2309A is available in two different configurations, as shown
in the ordering information table. The NB2309A1 is the base part. The
NB2309AI1H is the high drive version of the - and its rise and fall
-1
times are much faster than - part.
-1
Features
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MARKING
DIAGRAMS*
16
1
SOIC-
-16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP-
-16
DT SUFFIX
CASE 948F
XXXX
XXXX
ALYWG
G
1
16
XXXXXXXXG
AWLYWW
15 MHz to 133 MHz Operating Range, Compatible with CPU and
PCI Bus Frequencies
Zero Input - Output Propagation Delay
-
Multiple Low-
-Skew Outputs
Output-
-Output Skew Less than 250 ps
Device-
-Device Skew Less than 700 ps
One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
Less than 200 ps Cycle- -Cycle Jitter is Compatible with
-to-
PentiumR Based Systems
Test Mode to Bypass PLL
Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
3.3 V Operation, Advanced 0.35
m
CMOS Technology
Guaranteed Across Commercial and Industrial Temperature Ranges
These are Pb-
-Free Devices
XXXX = Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
W, WW = Work Week
G or
G
= Pb--Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in
the package dimensions section on page 7 of this data sheet.
Semiconductor Components Industries, LLC, 2010
October, 2010 - Rev. 10
-
1
Publication Order Number:
NB2309A/D
NB2309A
PLL
REF
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
S2
SELECT INPUT
DECODING
S1
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Figure 1. Block Diagram
Table 1. SELECT INPUT DECODING
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
-
Three--state
Driven
Driven
Driven
Clock B1 - B4
-
Three--state
Three--state
Driven
Driven
CLKOUT
(Note 1)
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL
ShutDown
N
N
Y
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the output.
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2
NB2309A
REF
CLKA1
CLKA2
1
2
3
4
16
15
14
13
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
V
DD
GND
NB2309A
5
6
7
8
12
11
10
9
CLKB1
CLKB2
S2
Figure 2. Pin Configuration
Table 2. PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF (Note 2)
CLKA1 (Note 3)
CLKA2 (Note 3)
V
DD
GND
CLKB1 (Note 3)
CLKB2 (Note 3)
S2 (Note 4)
S1 (Note 4)
CLKB3 (Note 3)
CLKB4 (Note 3)
GND
V
DD
CLKA3 (Note 3)
CLKA4 (Note 3)
CLKOUT (Note 3)
Description
Input reference frequency, 5 V tolerant input.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
3.3 V supply.
Ground.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Select input, bit 2.
Select input, bit 1.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Ground.
3.3 V supply.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
Buffered output, internal feedback on this pin.
2. Weak pulldown.
3. Weak pulldown on all outputs.
4. Weak pullup on these inputs.
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NB2309A
Table 3. MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Maximum Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (per MIL--STD--883, Method 3015)
Min
--0.5
--0.5
--0.5
--65
Max
+7.0
V
DD
+ 0.5
7
+150
260
150
>2000
Unit
V
V
V
C
C
C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. OPERATING CONDITIONS
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Industrial
Commercial
Description
Min
3.0
--40
0
Max
3.6
85
70
30
10
7
Unit
V
C
pF
pF
pF
Table 5. ELECTRICAL CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
DD
Description
Input LOW Voltage (Note 5)
Input HIGH Voltage (Note 5)
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current (Commercial Temp)
Supply Current (Industrial Temp)
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (--1)
I
OL
= 12 mA (--1H)
I
OH
= --8 mA (--1)
I
OH
= --12 mA (--1H)
Unloaded outputs at 66.67 MHz,
Select inputs at V
DD
Unloaded outputs at
100 MHz
66.67 MHz
33 MHz
Select inputs at V
DD
or GND, at Room
Temp
2.4
34
50
34
19
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
mA
mA
V
V
mA
mA
5. REF input has a threshold voltage of V
DD
/2.
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4
NB2309A
Table 6. SWITCHING CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C (Note 6)
Parameter
1/t
1
1/t
1
t
3
t
4
t
5
t
6
t
7
t
8
t
J
t
LOCK
Description
Output Frequency
Duty Cycle = (t
2
/ t
1
) * 100
Output Rise Time
Output Fall Time
Output--to--Output Skew
Delay, REF Rising Edge to CLKOUT
Rising Edge
Device--to--Device Skew
Output Slew Rate
Cycle--to--Cycle Jitter
PLL Lock Time
(--1, --1H)
(--1H)
(--1)
(--1H)
30 pF load
10 pF load
Measured at 1.4 V, F
OUT
= 66.67 MHz
< 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 2.0 V and 0.8 V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins of
the device
Measured between 0.8 V and 2.0 V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
1
200
1.0
0
0
Test Conditions
Min
15
15
40
45
50
50
Typ
Max
100
133
60
55
2.5
1.5
1.5
250
350
700
Unit
MHz
%
ns
ns
ps
ps
ps
V/ns
ps
ms
6. All parameters specified with loaded outputs in PLL--Mode.
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