THIS SPEC IS OBSOLETE
Spec No: 001-08350
Spec Title: CY7C1061DV18, 16-MBIT (1M X 16) STATIC RAM
Replaced by:
None
CY7C1061DV18
16-Mbit (1M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
■
Functional Description
The CY7C1061DV18 is a high performance CMOS Static RAM
(SRAM) organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE
1
LOW and CE
2
HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
),
is written into the location specified on the address pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O
8
through I/O
15
) is written into the location specified
on the address pins (A
0
through A
19
).
To read from the device, enable the chip by taking CE
1
LOW and
CE
2
HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appears on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then
data from memory appears on I/O
8
to I/O
15
. See the
Truth Table
on page 11
for a complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a high
impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1061DV18 is available in a 54-pin TSOP II pinout.
For a complete list of related documentation,
click here.
High Speed
❐
t
AA
= 15 ns
Low Active Power
❐
I
CC
= 150 mA at 67 MHz
Low complementary metal oxide semiconductor (CMOS)
Standby Power
❐
I
SB2
= 25 mA
Operating voltages of 1.7 V to 2.2 V
1.5 V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL) compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free 54-pin thin small outline package (TSOP)
Type II package
■
■
■
■
■
■
■
■
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
SENSE AMPS
1M x 16
ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN
DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
BHE
WE
OE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document Number: 001-08350 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 28, 2016
CY7C1061DV18
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 001-08350 Rev. *L
Page 2 of 17
CY7C1061DV18
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
-15
15
150
25
Unit
ns
mA
mA
Pin Configurations
Figure 1. 54-pin TSOP II pinout (Top View)
I/O
12
V
CC
I/O
13
I/O
14
V
SS
I/O
15
A
4
A
3
A
2
A
1
A
0
BHE
CE
1
V
CC
WE
CE
2
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
I/O
2
V
SS
I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
I/O
11
V
SS
I/O
10
I/O
9
V
CC
I/O
8
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
NC
BLE
A
10
A
11
A
12
A
13
A
14
I/O
7
V
SS
I/O
6
I/O
5
V
CC
I/O
4
Document Number: 001-08350 Rev. *L
Page 3 of 17
CY7C1061DV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature
with power applied ................................... –55
C
to +125
C
Supply voltage
on V
CC
to relative GND
[1]
.........................–0.2 V to +2.45 V
DC voltage applied to outputs
in High Z state
[1]
.......................................–0.2 V to +2.45 V
DC input voltage
[1]
....................................–0.2 V to +2.45 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ........................... >2001 V
Latch-up current ..................................................... >200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40
C
to +85
C
V
CC
1.7 V to 2.2 V
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[1]
Input leakage current
Output leakage current
V
CC
operating supply current
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, output disabled
Max V
CC
, f = f
MAX
= 1/t
RC
,
I
OUT
= 0 mA CMOS levels
CE
1
> V
IH
, CE
2
< V
IL,
Max V
CC
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
CE
1
> V
CC
– 0.2 V, CE
2
< 0.2 V,
Max V
CC
, V
IN
> V
CC
– 0.2 V, or V
IN
< 0.2 V, f = 0
Test Conditions
Min V
CC
, I
OH
= –0.1 mA
Min V
CC
, I
OL
= 0.1 mA
-15
Min
1.4
–
1.4
–0.2
–1
–1
–
–
–
Max
–
0.2
V
CC
+ 0.2
0.4
+1
+1
150
30
25
Unit
V
V
V
V
A
A
mA
mA
mA
Note
1. V
IL
(min) = –2.0 V for pulse durations of less than 20 ns.
Document Number: 001-08350 Rev. *L
Page 4 of 17
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