NB2305A
3.3 V Zero Delay
Clock Buffer
The NB2305A is a versatile, 3.3 V zero delay buffer designed to
distribute high-
-speed clocks. It accepts one reference input and drives
out five low-
-skew clocks. It is available in a 8 pin package.
The -
-1H version of the NB2305A operates at up to 133 MHz, and
has higher drive than the - devices. All parts have on-
-1
-chip PLL’s that
lock to an input clock on the REF pin. The PLL feedback is on-
-chip
and is obtained from the CLKOUT pad.
Multiple NB2305A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle- -cycle jitter. The input
-to-
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2305A is available in two different configurations, as shown
in the ordering information table. The NB2305AI is the base part. The
NB2305AI1H is the high drive version of the - and its rise and fall
-1
times are much faster than - part.
-1
Features
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MARKING
DIAGRAMS*
8
1
SOIC-
-8
D SUFFIX
CASE 751
1
8
XXXX
ALYW
G
8
8
1
TSSOP-
-8
DT SUFFIX
CASE 948S
XXXX
A
L
Y
W
G
1
XXX
YWW
A
G
15 MHz to 133 MHz Operating Range, Compatible with CPU and
PCI Bus Frequencies
Zero Input - Output Propagation Delay
-
Multiple Low-
-Skew Outputs
Output-
-Output Skew Less than 250 ps
Device-
-Device Skew Less than 700 ps
One Input Drives 5 Outputs
Less than 200 ps Cycle- -Cycle Jitter is Compatible with
-to-
PentiumR Based Systems
Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm
3.3 V Operation, Advanced 0.35
m
CMOS Technology
Guaranteed Across Commercial and Industrial Temperature Ranges
These are Pb-
-Free Devices
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb--Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Semiconductor Components Industries, LLC, 2010
October, 2010 - Rev. 10
-
1
Publication Order Number:
NB2305A/D
NB2305A
REF
PLL
CLKOUT
REF
CLK2
CLK2
CLK1
CLK3
GND
3
4
1
2
8
7
CLKOUT
CLK4
V
DD
CLK3
CLK1
NB2305A
6
5
CLK4
Figure 1. Block Diagram
Figure 2. Pin Configuration
Table 1. PIN DESCRIPTION
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF (Note1)
CLK2 (Note 2)
CLK1 (Note 2)
GND
CLK3 (Note 2)
V
DD
CLK4 (Note 2)
CLKOUT (Note 2)
Input reference frequency, 5 V tolerant input.
Buffered clock output.
Buffered clock output.
Ground.
Buffered clock output.
3.3 V supply.
Buffered clock output.
Buffered clock output, internal feedback on this pin.
1. Weak pulldown.
2. Weak pulldown on all outputs.
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NB2305A
Table 2. MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Maximum Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (per MIL--STD--883, Method 3015)
Min
--0.5
--0.5
--0.5
--65
Max
+7.0
V
DD
+ 0.5
7.0
+150
260
150
>2000
Unit
V
V
V
C
C
C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. OPERATING CONDITIONS FOR INDUSTRIAL TEMPERATURE DEVICES
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Industrial
Commercial
Description
Min
3.0
--40
0
Max
3.6
85
70
30
10
7
Unit
V
C
pF
pF
pF
Table 4. ELECTRICAL CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
DD
Description
Input LOW Voltage (Note 3)
Input HIGH Voltage (Note 3)
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current (Commercial Temp)
Supply Current (Industrial Temp)
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (--1)
I
OL
= 12 mA (--1H)
I
OH
= --8 mA (--1)
I
OH
= --12 mA (--1H)
Unloaded outputs at 66.67 MHz,
Select inputs at V
DD
Unloaded outputs at
100 MHz
66.67 MHz
33 MHz
Select inputs at V
DD
or GND, at Room
Temp
2.4
34
50
34
19
2.0
50
100
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
mA
mA
V
V
mA
mA
3. REF input has a threshold voltage of V
DD
/2.
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NB2305A
Table 5. SWITCHING CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C (Note 4)
Parameter
1/t
1
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Description
Output Frequency
Duty Cycle = (t
2
/ t
1
) * 100
Output Rise Time
Output Fall Time
Output--to--Output Skew
Delay, REF Rising Edge to CLKOUT
Rising Edge
Device--to--Device Skew
Cycle--to--Cycle Jitter
PLL Lock Time
(--1, --1H)
(--1H)
(--1)
(--1H)
(--1)
(--1H)
30 pF load
10 pF load
Measured at 1.4 V, F
OUT
= 66.67 MHz
< 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 2.0 V and 0.8 V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins of
the device
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
0
0
Test Conditions
Min
15
15
40
45
50
50
Typ
Max
100
133
60
55
2.5
1.5
2.5
1.5
250
350
700
200
1.0
Unit
MHz
%
ns
ns
ps
ps
ps
ps
ms
4. All parameters specified with loaded outputs.
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NB2305A
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-
-output delay.
For applications requiring zero input-
-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-
-input-
-output
delay.
SWITCHING WAVEFORMS
t
1
t
2
1.4 V
1.4 V
1.4 V
2.0 V
OUTPUT
0.8 V
t
3
2.0 V
0.8 V
t
4
0V
3.3 V
Figure 3. Duty Cycle Timing
Figure 4. All Outputs Rise/Fall Time
OUTPUT
OUTPUT
1.4 V
1.4 V
t
5
INPUT
OUTPUT
t
6
V
DD
2
V
DD
2
Figure 5. Output - Output Skew
-
Figure 6. Input - Output Propagation Delay
-
CLKOUT, Device 1
CLKOUT, Device 2
t
7
V
DD
2
V
DD
2
Figure 7. Device - Device Skew
-
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