CY7C1021BNV33
64 K × 16 Static RAM
64 K × 16 Static RAM
Features
■
■
Functional Description
The CY7C1021BNV33
[1]
is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into
the location specified on the address pins (A
0
through A
15
). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into the location specified on the address
pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O
8
to I/O
15.
See the truth table
at the back of this data sheet for a complete description of read
and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW,
and WE LOW).
The CY7C1021BNV33 is available in standard 44-pin TSOP
Type II and 48-ball mini BGA packages.a
For a complete list of related documentation, click
here.
3.3 V operation (3.0 V–3.6 V)
High speed
❐
t
AA
= 15 ns
CMOS for optimum speed/power
Low Active Power
❐
576 mW (max)
Low CMOS Standby Power
❐
1.80 mW (max)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II and 48-ball Mini BGA package
■
■
■
■
■
■
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 001-06433 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 16, 2015
CY7C1021BNV33
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Selection Guide
-15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
15
160
0.5
Document Number: 001-06433 Rev. *F
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Page 2 of 18
CY7C1021BNV33
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 5
AC Test Loads and Waveforms ....................................... 6
Switching Characteristics ................................................ 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
Document Number: 001-06433 Rev. *F
Page 3 of 18
CY7C1021BNV33
Pin Configurations
TSOP II
Top View
A
4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
V
SS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
V
SS
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Mini BGA
Top View
1
BLE
2
OE
3
A
0
4
A
1
5
A
2
CE
I/O
1
6
NC
I/O
0
I/O
2
A
B
C
D
E
F
G
H
I/O
8
BHE
I/O
9
I/O
10
A
3
A
5
A
4
A
6
A
7
NC
V
SS
I/O
11
NC
V
CC
I/O
12
NC
I/O
14
I/O
13
A
14
I/O
15
NC
NC
A
8
A
12
A
9
I/O
3
V
CC
I/O
4
V
SS
I/O
6
A
15
I/O
6
A
13
A
10
WE I/O
7
A
11
NC
Document Number: 001-06433 Rev. *F
Page 4 of 18
CY7C1021BNV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on
V
CC
to Relative GND
[2]
...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State
[2]
................................ –0.5 V to V
CC
+ 0.5 V
DC Input Voltage
[2]
............................ –0.5 V to V
CC
+ 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-Up Current ................................................... > 200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40 °C to +85 °C
V
CC
3.3 V
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CE Power Down
Current – TTL Inputs
Automatic CE Power Down
Current – CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
, Output Disabled
V
CC
= Max, I
OUT
= 0 mA, f = f
MAX
= 1/t
RC
Max V
CC
, CE > V
IH
, V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 8.0 mA
-15
Min
2.4
–
2.2
–0.3
–1
–1
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
160
40
500
Unit
V
V
V
V
A
A
mA
mA
A
Capacitance
Parameter
[3]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz
Max
6
8
Unit
pF
pF
Notes
2. Minimum voltage is –2.0 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-06433 Rev. *F
Page 5 of 18
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