AN-225: 12-Bit Voltage-Output DACs for Single-Supply 5V
and 12V Systems
Data Sheet
•
AD7244: LC2MOS Dual, Complete, 12-Bit/14-Bit Serial
DACs Data Sheet
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REFERENCE MATERIALS
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AD7242/AD7244–SPECIFICATIONS
All Specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Full-Scale Error
2
Negative Full-Scale Error
2
REFERENCE OUTPUT
3
REF OUT @ +25°C
T
MIN
to T
MAX
REF OUT Tempco
Reference Load Change
(ΔREF OUT vs.
ΔI)
REFERENCE INPUTS
REF INA, REF INB Input Range
Input Current
LOGIC INPUTS
(LDACA,
LDACB, TFSA, TFSB,
TCLKA, TCLKB, DTA, DTB)
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
ANALOG OUTPUTS
(V
OUTA
, V
OUTB
)
Output Voltage Range
DC Output Impedance
Short Circuit Current
AC CHARACTERISTICS
4
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Channel-to-Channel Isolation
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
Total Power Dissipation
AD7242
J, A Versions
1
K, B Versions
1
12
±
1
±
1
±
5
±
5
±
5
2.99/3.01
2.98/3.02
35
–1
2.85/3.15
1
12
±
1/2
±
1
±
5
±
5
±
5
2.99/3.01
2.98/3.02
35
–1
2.85/3.15
1
(V
DD
= +5 V 5% V
SS
= –5 V 5%, AGND = DGND = 0 V, REF INA =
REF INB = +3 V. V
OUTA
, V
OUTB
load to AGND: R
L
= 2 k , C
L
= 100 pF.
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V min/V max
V min/V max
ppm/°C typ
mV max
V min/V max
μA
max
Test Conditions/Comments
Guaranteed Monotonic
Reference Load Current Change (0
μA–500 μA)
3 V
±
5%
2.4
0.8
±
10
10
2.4
0.8
±
10
10
V min
V max
μA
max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
±
3
0.1
20
±
3
0.1
20
V nom
Ω
typ
mA typ
Settling Time to Within
±
1/2 LSB of Final Value
Typically 2
μs
Typically 2
μs
DAC Code Change All 1s to All 0s
V
OUT
= 10 kHz Sine Wave
±
5% for Specified Performance
±
5% for Specified Performance
Cumulative Current from the Two V
DD
Pins
Cumulative Current from the Two V
SS
Pins
Typically 130 mW
3
3
10
2
110
+5
–5
27
15
195
3
3
10
2
110
+5
–5
27
15
195
μs
max
μs
max
nV secs typ
nV secs typ
dB typ
V nom
V nom
mA max
mA max
mW max
NOTES
1
Temperature ranges are as follows: J, K Versions: –40°C to +85°C; A, B Versions: –40°C to +85°C.
2
Measured with respect to REF IN and includes bipolar offset error.
3
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
4
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV.
B
AD7244
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Full-Scale Error
2
Negative Full-Scale Error
2
REFERENCE OUTPUT
3
REF OUT @ +25°C
T
MIN
to T
MAX
REF OUT Tempco
Reference Load Change
(ΔREF OUT vs.
ΔI)
REFERENCE INPUTS
REF INA, REF INB Input Range
Input Current
LOGIC INPUTS
(LDACA,
LDACB, TFSA, TFSB,
TCLKA, TCLKB, DTA, DTB)
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
ANALOG OUTPUTS
(V
OUTA
, V
OUTB
)
Output Voltage Range
DC Output Impedance
Short Circuit Current
AC CHARACTERISTICS
4
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Channel-to-Channel Isolation
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
Total Power Dissipation
AD7244
J, A Versions
1
S Version
1
14
±
2
±
1
±
10
±
10
±
10
2.99/3.01
2.98/3.02
35
–1
2.85/3.15
1
14
±
2
±
1
±
10
±
10
±
10
2.99/3.01
2.98/3.02
35
–1
2.85/3.15
1
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V min/V max
V min/V max
ppm/°C typ
mV max
V min/V max
μA
max
Reference Load Current Change (0
μA–500 μA)
3 V
±
5%
Test Conditions/Comments
Guaranteed Monotonic
2.4
0.8
±
10
10
2.4
0.8
±
10
10
V min
V max
μA
max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
±
3
0.1
20
±
3
0.1
20
V nom
Ω
typ
mA typ
Settling Time to Within
±
1/2 LSB of Final Value
Typically 2.5
μs
Typically 2.5
μs
DAC Code Change All 1s to All 0s
V
OUT
= 10 kHz Sine Wave
±
5% for Specified Performance
±
5% for Specified Performance
Cumulative Current from the Two V
DD
Pins
Cumulative Current from the Two V
SS
Pins
Typically 130 mW
4
4
10
2
110
+5
–5
27
15
195
4
4
10
2
110
+5
–5
28
15
205
μs
max
μs
max
nV secs typ
nV secs typ
dB typ
V nom
V nom
mA max
mA max
mW max
NOTES
1
Temperature ranges are as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2
Measured with respect to REF IN and includes bipolar offset error.
3
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
4
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
REV.
B
–3–
AD7244
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
1
t
2
t
3 3
t
4
t
5
t
6
Limit at T
MIN
, T
MAX
(J, K, A, B Versions)
50
75
150
30
75
40
DD
= +5 V
5%, V
SS
= –5 V
5%, AGND = DGND = 0 V)
Units
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
TFS
to TCLK Falling Edge
TCLK Falling Edge to
TFS
TCLK Cycle Time
Data Valid to TCLK Setup Time
Data Valid to TCLK Hold Time
LDAC
Pulse Width
Limit at T
MIN
, T
MAX
(S Version)
50
100
200
40
100
40
NOTES
1
Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-
age level of 1.6 V.
2
See Figure 6.
3
TCLK Mark/Space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
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