60A Exposed Top Integrated PowIRstage®
FEATURES
Peak efficiency up to 95% at 1.2V
Integrated driver, control MOSFET, synchronous
MOSFET and Schottky diode
Input voltage (VIN) operating range up to 15V
Output voltage range from 0.25V to Vcc-2.5V, or to
5.5V if internal current sense amplifier is not used
Output current capability of 60A DC
Operation up to 1.0MHz
Integrated current sense amplifier
VCC under voltage lockout
Thermal flag
Body-Braking® load transient support
Diode-emulation high efficiency mode
Compatible with 3.3V PWM logic and VCC tolerant
Compliant with Intel DrMOS V4.0
PCB footprint compatible with IR3550 and IR3551
Enhanced top side cooling through exposed pad
Small 6mm x 6mm x 0.9mm PQFN package
Lead free RoHS compliant package
IR3575
DESCRIPTION
The IR3575 exposed-top integrated PowIRstage® is a
synchronous buck gate driver co-packed with a control
MOSFET and a synchronous MOSFET with integrated
Schottky diode. It is optimized internally for PCB layout,
heat transfer and driver/MOSFET timing. Custom designed
gate driver and MOSFET combination enables higher
efficiency at lower output voltages required by cutting
edge CPU, GPU and DDR memory designs.
Up to 1.0MHz switching frequency enables high
performance transient response, allowing miniaturization
of output inductors, as well as input and output capacitors
while maintaining industry leading efficiency. The IR3575’s
superior efficiency enables smallest size and lower solution
cost. The IR3575 PCB footprint is compatible with the
IR3550 (60A), IR3551 (50A) and IR3553 (40A).
Integrated current sense amplifier achieves superior
current sense accuracy and signal to noise ratio vs. best-in-
class controller based Inductor DCR sense methods.
The IR3575 incorporates the Body-Braking® feature which
enables reduction of output capacitors. Synchronous diode
emulation mode in the IR3575 removes the zero-current
detection burden from the PWM controller and increases
system light-load efficiency.
The IR3575 is optimized specifically for CPU core power
delivery in server applications. The ability to meet the
stringent requirements of the server market also makes
the IR3575 ideally suited to powering GPU and DDR
memory designs and other high current applications.
APPLICATIONS
Voltage Regulators for CPUs, GPUs, and DDR
memory arrays
High current, low profile DC-DC converters
BASIC APPLICATION
VCC
4.5V to 7V
95
93
91
20
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
40
45
50
55
60
BOOST
PHSFLT#
PWM
BBRK#
REFIN
IOUT
PHSFLT#
PWM
BBRK#
REFIN
IOUT
LGND
CSIN+
CSIN-
PGND
SW
VOUT
Efficiency (%)
4.5V to 15V
87
85
83
81
79
77
75
Output Current (A)
Figure 2: Typical IR3575 Efficiency & Power Loss
(See Note 2 on Page 8)
Figure 1: IR3575 Basic Application Circuit
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September 6, 2017 | DATASHEET V3.4
Power Loss (W)
VCC
IR3575
89
VIN
VIN
60A Exposed Top Integrated PowIRstage®
PINOUT DIAGRAM
IR3575
ORDERING INFORMATION
Package
PQFN, 32 Lead
6mm x 6mm
Package
PQFN, 32 Lead
6mm x 6mm
Tape & Reel Qty
3000
Qty
100
Part Number
IR3575MTRPBF
Part Number
IR3575MPBF
Figure 3: IR3575 Pin Diagram, Top View
TYPICAL APPLICATION DIAGRAM
VCC
4.5V to 7V
R1
10k
C3
1uF
3
18-23
VIN
24
C1
0.1uF
C2
10uF x 2
VIN
4.5V to 15V
IR3575
25
26
27
C9
22nF
VCC
PHSFLT#
PWM
BBRK#
Optional for
diode emulation
setup
PHSFLT#
PWM
BBRK#
LGND
REFIN
IOUT
TGND
CSIN-
2
CSIN+
Gate
Drivers
and
Current
Sense
Amplifier
BOOST
SW
6-15
R2
2.49k
C4
0.22uF
C5
0.22uF
L1
150nH
C6
22uF
C7
470uF
VOUT
28
29
30
REFIN
C8
1nF
PGND 16, 17
PGND 4
IOUT
31
1
No Connect
Figure 4: Application Circuit with Current Sense Amplifier
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September 6, 2017 | DATASHEET V3.4
60A Exposed Top Integrated PowIRstage®
TYPICAL APPLICATION DIAGRAM (CONTINUED)
VCC
4.5V to 7V
R1
10k
C3
0.22uF
IR3575
VIN
4.5V to 15V
3
VCC
18-23
VIN
24
C1
0.1uF
C2
10uF x 2
IR3575
25
26
27
28
29
30
PHSFLT#
PWM
BBRK#
LGND
REFIN
IOUT
PHSFLT#
PWM
BBRK#
BOOST
Gate
Drivers
and
Current
Sense
Amplifier
SW
C5
0.22uF
L1
150nH
C6
22uF
C7
470uF
6-15
R2
2.49k
C4
0.22uF
VOUT
PGND 16, 17
PGND 4
CSIN-
2
CSIN+
CS+
CS-
TGND
1
31
No Connect
Figure 5: Application Circuit without Current Sense Amplifier
FUNCTIONAL BLOCK DIAGRAM
BOOST
24
VIN
18
VIN
19
VIN
20
VIN
21
VIN
22
VIN
23
IR3575
VCC
3
3.3V
200k
VCC
6
7
Driver
8
9
Diode
Emulation
Comparator
SW
SW
SW
SW
BBRK#
27
POR
S
R
Q
3.3V
PWM
26
MOSFET
& Thermal
Detection
Current Sense
Amplifier
+
PHSFLT# 25
LGND
28
Power-on
Reset
(POR),
3.3V
Reference,
and
Dead-time
Control
10 SW
11 SW
12 SW
18k
-
+
VCC
13 SW
14 SW
15 SW
Offset +
-
Driver
IOUT
REFIN
30
29
-
1
2
4
31
5
32
16
17
CSIN- CSIN+ PGND TGND
GATEL GATEL
PGND PGND
Figure 6: IR3575 Functional Block Diagram
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September 6, 2017 | DATASHEET V3.4
60A Exposed Top Integrated PowIRstage®
PIN DESCRIPTIONS
PIN #
1
2
3
4, 16, 17
5, 32
6 – 15
18 – 23
IR3575
PIN NAME
CSIN-
CSIN+
VCC
PGND
GATEL
SW
VIN
PIN DESCRIPTION
Inverting input to the current sense amplifier. Connect to LGND if the current sense
amplifier is not used.
Non-Inverting input to the current sense amplifier. Connect to LGND if the current sense
amplifier is not used.
Bias voltage for control logic. Connect a minimum 1uF cap between VCC and PGND (pin
4) if current sense amplifier is used. Connect a minimum 0.22uF cap between VCC and
PGND (pin 4) if current sense amplifier is not used.
Power ground of MOSFET driver and the synchronous MOSFET. MOSFET driver signal is
referenced to this pin.
Low-side MOSFET driver pins that can be connected to a test point in order to observe
the waveform.
Switch node of synchronous buck converter.
High current input voltage connection. Recommended operating range is 4.5V to 15V.
Connect at least two 10uF 1206 ceramic capacitors and a 0.22uF 0402 ceramic
capacitor. Place the capacitors as close as possible to VIN pins and PGND pins (16-17).
The 0.22uF 0402 capacitor should be on the same side of the PCB as the IR3575.
Bootstrap capacitor connection. The bootstrap capacitor provides the charge to turn on
the control MOSFET. Connect a minimum 0.22µF capacitor from BOOST to SW pin. Place
the capacitor as close to BOOST pin as possible and minimize parasitic inductance of
PCB routing from the capacitor to SW pin.
Open drain output of the phase fault circuits. Connect to an external pull-up resistor.
Output is low when a MOSFET fault or over temperature condition is detected.
3.3V logic level tri-state PWM input and 7V tolerant. “High” turns the control MOSFET
on, and “Low” turns the synchronous MOSFET on. “Tri-state” turns both MOSFETs off in
Body-Braking® mode. In diode emulation mode, “Tri-state” activates internal diode
emulation control. See “PWM Tri-state Input” Section for further details about the PWM
Tri-State functions.
3.3V logic level input and 7V tolerant with internal weak pull-up to 3.3V. Logic low
disables both MOSFETs. Pull up to VCC directly or by a 4.7kΩ resistor if Body-Braking® is
not used. The second function of the BBRK# pin is to select diode emulatiom mode.
Pulling BBRK# low at least 20ns after VCC passes its UVLO threshold selects internal
diode emulation control. See “Body-Braking® Mode” Section for further details.
Signal ground. Driver control logic, analog circuits and IC substrate are referenced to
this pin.
Reference voltage input from the PWM controller. IOUT signal is referenced to the
voltage on this pin. Connect to LGND if the current sense amplifier is not used.
Current output signal. Voltage on this pin is equal to V(REFIN) + 32.5 * [V(CSIN+) –
V(CSIN-)]. Float this pin if the current sense amplifier is not used.
This pin is connected to internal power and signal ground of the driver. For best
performance of the current sense amplifier, TGND must be electrically isolated from
Power Ground (PGND) and Signal Ground (LGND) in the PCB layout. Connect to PGND if
the current sense amplifier is not used.
Exposed pad on top side of the package. Connect to a heat sink through insulated
thermal material to improve the thermal performance of the package.
24
BOOST
25
PHSFLT#
26
PWM
27
BBRK#
28
29
30
LGND
REFIN
IOUT
31
Exposed
Pad
TGND
SW
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September 6, 2017 | DATASHEET V3.4
60A Exposed Top Integrated PowIRstage®
ABSOLUTE MAXIMUM RATINGS
IR3575
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
PIN Number
1
2
3
4
5, 32
6-15
16, 17
18-23
24
25
26
27
28
29
30
31
PIN NAME
CSIN-
CSIN+
VCC
PGND
GATEL
SW
2
V
MAX
VCC + 0.3V
VCC + 0.3V
8V
0.3V
VCC + 0.3V
25V
NA
25V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-3V for 20ns,
-0.3V DC
-5V for 20ns,
-0.3V DC
NA
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
NA
15mA
1A for 100ns,
200mA DC
65A RMS,
90A Peak
30A RMS,
35A Peak
5A RMS
1A for 100ns,
100mA DC
1mA
1mA
1mA
15mA
1mA
5mA
NA
I
SINK
1mA
1mA
5A for 100ns,
200mA DC
15mA
1A for 100ns,
200mA DC
30A RMS,
35A Peak
65A RMS,
90A Peak
25A RMS,
30A Peak
5A for 100ns,
100mA DC
20mA
1mA
1mA
15mA
1mA
5mA
NA
PGND
VIN
2
BOOST
1
33V
VCC + 0.3V
VCC + 0.3V
VCC + 0.3V
0.3V
3.5V
VCC + 0.3V
0.3V
PHSFLT#
PWM
BBRK#
LGND
REFIN
IOUT
TGND
Note:
1. Maximum BOOST – SW = 8V.
2. Maximum VIN – SW = 25V.
3. All the maximum voltage ratings are referenced to PGND (Pins 16 and 17).
THERMAL INFORMATION
Thermal Resistance, Junction to Top (θ
JC_TOP
)
Thermal Resistance, Junction to PCB (pin 17) (θ
JB
)
Thermal Resistance (θ
JA
)
1
0.5 °C/W
1.7 °C/W
19.1 °C/W
-40 to 150°C
-65°C to 150°C
HBM Class 1B JEDEC Standard
3
260°C
Maximum Operating Junction Temperature
Maximum Storage Temperature Range
ESD rating
MSL Rating
Reflow Temperature
Note:
1. Thermal Resistance (θ
JA
) is measured with the component mounted on a high effective thermal conductivity test board in free air.
Refer to International Rectifier Application Note AN-994 for details.
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September 6, 2017 | DATASHEET V3.4
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