TSM1NB60
Taiwan Semiconductor
N-Channel Power MOSFET
600V, 1A, 10Ω
FEATURES
●
●
●
●
●
Advanced planar process
100% avalanche tested
Low R
DS(ON)
8Ω (Typ.)
Low gate charge typical @ 6.1 nC (Typ.)
Low Crss typical @4.2pF (Typ.)
KEY PERFORMANCE PARAMETERS
PARAMETER
V
DS
R
DS(on)
(max)
Q
g
VALUE
600
10
6.1
UNIT
V
Ω
nC
APPLICATION
●
●
●
Power Supply
Lighting
Charger
SOT-223
TO-251 (IPAK)
TO-252 (DPAK)
Notes:
MSL 3 (Moisture Sensitivity Level) for TO-252 (D-PAK), SOT-223 per J-STD-020
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
(Note 1)
SYMBOL
V
DS
V
GS
T
C
= 25°C
T
C
= 100°C
I
D
I
DM
P
DTOT
E
AS
I
AS
dv/dt
T
J
, T
STG
IPAK/DPAK
600
±30
1
0.7
4
39
5
1
4.5
SOT-223
UNIT
V
V
A
A
(Note 2)
Total Power Dissipation @ T
C
= 25°C
Single Pulsed Avalanche Energy
Single Pulsed Avalanche Current
Peak Diode Recovery dv/dt
(Note 4)
(Note 3)
(Note 3)
2.1
W
mJ
A
V/ns
°C
Operating Junction and Storage Temperature Range
- 55 to +150
THERMAL PERFORMANCE
PARAMETER
Junction to Case Thermal Resistance
Junction to Ambient Thermal Resistance
SYMBOL
R
ӨJC
R
ӨJA
IPAK/DPAK
2.87
110
SOT-223
--
60
UNIT
°C/W
°C/W
Notes:
R
ӨJA
is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined
at the solder mounting surface of the drain pins. R
ӨJA
is guaranteed by design while R
ӨCA
is determined by the user’s board
design. R
ӨJA
shown below for single device operation on FR-4 PCB in still air.
Document Number: DS_P0000038
1
Version: D1706
TSM1NB60
Taiwan Semiconductor
ELECTRICAL SPECIFICATIONS
(T
A
= 25°C unless otherwise noted)
PARAMETER
Static
(Note 5)
CONDITIONS
V
GS
= 0V, I
D
= 250µA
V
GS
= 10V, I
D
= 0.5A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 600V, V
GS
= 0V
V
GS
= ±30V, V
DS
= 0V
V
DS
= 10V, I
D
= 0.5A
SYMBOL
BV
DSS
R
DS(ON)
V
GS(TH)
I
DSS
I
GSS
g
fs
Q
g
MIN
600
--
2.5
--
--
--
TYP
--
8
3.5
--
--
0.8
MAX
--
10
4.5
10
±100
--
UNIT
V
Ω
V
µA
nA
S
Drain-Source Breakdown Voltage
Drain-Source On-State Resistance
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage
Forward Transfer Conductance
Dynamic
(Note 6)
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching
(Note 7)
--
--
--
--
--
--
--
6.1
1.4
3.3
138
17.1
4.2
12.5
--
--
--
--
--
--
--
Ω
pF
nC
V
DS
= 480V, I
D
= 1A,
V
GS
= 10V
Q
gs
Q
gd
C
iss
V
DS
= 25V, V
GS
= 0V,
f = 1.0MHz
F = 1MHz, open drain
C
oss
C
rss
R
g
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Source-Drain Diode
Source Current
Source Current (Pulse)
Notes:
1.
2.
3.
4.
5.
6.
7.
Current limited by package.
Pulse width limited by the maximum junction temperature.
L = 10mH, I
AS
= 1A, V
DD
= 50V, R
G
= 25Ω, Starting T
J
= 25 C.
I
SD
≤1A , V
DD
≤BV
DSS
, di/dt≤200A/us , Starting T
J
= 25 C.
Pulse test: PW ≤ 300µs, duty cycle ≤ 2%.
For DESIGN AID ONLY, not subject to production testing.
Switching time is essentially independent of operating temperature.
o
o
t
d(on)
V
DD
= 300V, R
G
=25Ω
I
D
= 1A, V
GS
= 10V
(Note 5)
--
--
--
--
7.7
6.8
15.3
14.9
--
--
--
--
ns
t
r
t
d(off)
t
f
Diode Forward Voltage
I
S
= 1A, V
GS
= 0V
Integral reverse diode
In the MOSFET
V
SD
I
S
I
SM
--
--
--
0.9
--
--
1.4
1
4
V
A
Document Number: DS_P0000038
2
Version: D1706
TSM1NB60
Taiwan Semiconductor
ORDERING INFORMATION
PART NO.
TSM1NB60CH C5G
TSM1NB60CP ROG
TSM1NB60CW RPG
PACKAGE
TO-251
TO-252
SOT-223
PACKING
75 pcs / Tube
2,500 pcs / 13” Reel
2,500 pcs / 13” Reel
Note:
1. Compliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/EC
2. Halogen-free according to IEC 61249-2-21 definition
Document Number: DS_P0000038
3
Version: D1706
TSM1NB60
Taiwan Semiconductor
PACKAGE OUTLINE DIMENSIONS
(Unit: Millimeters)
TO-251
MARKING DIAGRAM
Y
= Year Code
M
= Month Code for Halogen Free Product
O
=Jan
P
=Feb
Q
=Mar
R
=Apr
S
=May
T
=Jun
U
=Jul
V
=Aug
W
=Sep
X
=Oct
Y
=Nov
Z
=Dec
L
= Lot Code (1~9, A~Z)
1NB60
YML
Document Number: DS_P0000038
4
Version: D1706
TSM1NB60
Taiwan Semiconductor
PACKAGE OUTLINE DIMENSIONS
(Unit: Millimeters)
TO-252
SUGGESTED PAD LAYOUT
MARKING DIAGRAM
Y
= Year Code
M
= Month Code for Halogen Free Product
O
=Jan
P
=Feb
Q
=Mar
R
=Apr
S
=May
T
=Jun
U
=Jul
V
=Aug
W
=Sep
X
=Oct
Y
=Nov
Z
=Dec
L
= Lot Code (1~9, A~Z)
1NB60
YML
Document Number: DS_P0000038
5
Version: D1706
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