Setting of any output voltage enabled (external resistors required)
•
High efficiency: 90% at IOUT=1A, VO=3.3V
•
Miniature package: HSSOP14
•
Soft start function
•
Standby mode
•
Overcurrent protection
•
Thermal shutdown
•
Fixed frequency: 180kHz
Applications
•
LCD TVs
•
Game machines
Semiconductor Components Industries, LLC, 2013
August, 2013
13107 MS IM 20070112-S00004 No.A0663-1/7
LV5781
Specifications
Absolute Maximum Ratings
at Ta=25°C
Parameter
Maximum input voltage
Maximum CBOOT pin voltage
Maximum SW pin voltage
Maximum voltage between CBOOT and
SW pins
Maximum voltage at FB, SS, and
ENABLE pins
Junction temperature
Allowable power dissipation
Operating temperature range
Storage temperature range
Tj max
Pd max
Topr
Tstg
Mounted on a circuit board *1
Vfs max
Symbol
VIN max
VBT max
VSW max
VBS max
Conditions
Ratings
6.5
13
6.5
6.5
6.5
125
0.85
-30 to +80
-40 to +125
Unit
V
V
V
V
V
°C
W
°C
°C
*1: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy.
*2: To ensure that the maximum voltage is not exceeded even for an instant, check that the coil voltage and other surge voltage levels are factored in.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Conditions
at Ta=25°C
Parameter
VIN pin voltage
CBOOT pin voltage
SW pin voltage
FB, SS, and ENABLE pin voltage
Symbol
VIN
VBT
VSW
VFSO
Conditions
Ratings
4.5 to 6
0 to 6
6
6
Unit
V
V
V
V
Electrical Characteristics
at Ta=25°C, VIN=5V (Unless specifically specified)
Parameter
Output voltage 1
Output voltage 2
Standby mode IC consumption current
Operating time IC consumption current
ENABLE high level voltage
ENABLE low level voltage
Efficiency
Reference voltage
FB pin bias current
On resistance
Soft start current
Oscillation frequency
Maximum on duty ratio
Current limiting value
Under voltage detection
Under voltage detection hysteresis
Thermal shutdown temperature
Thermal shutdown temperature
hysteresis
*These are design guarantee values and no measurements are made.
Symbol
VOUT1
VOUT2
ICC1
ICC2
VENH
VENL
Effcy
Vref
Iref
Ron
ISS
Fosc
D max
Icl
Vl
Vlh
Ttsd
Dtsd
Design guarantee value*
Design guarantee value*
CBOOT=5V
3
145
85
4.1
3.3
0.15
3.7
0.185
180
20
4.2
0.25
IOUT=1A, VO=3.3V
VIN=4.5V to 6V(±2%)
0.76
90
0.8
50
80
6.5
180
13
225
0.84
200
Conditions
min
FB2 pin selected
Dependent on the external voltage divider
ENABLE=0V
ENABLE=3V
3
0.7
3.2
0.85
1
2
10
5
Ratings
typ
3.3
max
3.4
V
V
μA
mA
V
V
%
V
nA
mΩ
μA
kHz
%
A
V
V
°C
°C
Unit
No.A0663-2/7
LV5781
Package Dimensions
unit : mm (typ)
3313
1.0
Pd max -- Ta
Mounted on a specified board:
114.3mm×76.1mm×1.6mm, glass epoxy
14
8
Allowable power dissipation, Pd max - W
6.5
0.85
0.8
4.4
6.4
0.6
0.5
1
1.3
(2.35)
0.65
7
0.22
0.4
0.38
0.15
0.2
1.5max
0.1 (1.3)
0
-40
-20
0
20
40
60
80
100
Ambient temperature, Ta - °C
1.5
SANYO : HSSOP14(225mil)
Block Diagram and Sample Application Circuits
CBOOT
VIN
BOOT(SW+VIN)
Pre-Drive
FB_GND
FB0
FB1
FB2
OERRAMP
6.5μA
S/D
OCP
OSC
180kHz
Error
Amp
PWM
comparator
SW
VOUT
SS
3.2V
Enable Internal
Reg
ON
OFF
GND
Vref
1.25V
UVLO
S/D
TSD
S/D
No.A0663-3/7
LV5781
Pin Assignment and Sample Application Circuits
G
N
D
1 FB_GND
ON
2 ENABLE
OFF
3 SS
4 FB1
5 VIN
6 SW
7 PGND
G
N
D
FB0 14
FB2 13
OERRAMP 12
CBOOT 11
VIN 10
SW 9
VIN 8
3.3V
Sample Application Circuit 1
G
N
D
1 FB_GND
ON
2 ENABLE
OFF
3 SS
4 FB1
5 VIN
6 SW
7 PGND
G
N
D
FB0 14
FB2 13
OERRAMP 12
CBOOT 11
VIN 10
SW 9
VIN 8
VOUT
Sample Application Circuit 2
*The capacitor between the FB0 and VOUT pins and capacitor between the OERRAMP pin and GND (the capacitors
shown inside the broken lines in the diagram) are used for phase compensation. Their capacitance is intended to stop
oscillation when oscillation is caused by the status of the output capacitor. As such, they can be left open under normal
circumstances.
No.A0663-4/7
LV5781
Pin Functions
Pin No.
1
2
3
4
5, 8, 10
6, 9
7
11
12
13
14
Pin name
FB_GND
ENABLE
SS
FB1
VIN
SW
PGND
CBOOT
OERRAMP
FB2
FB0
Description
GND of output voltage setting pins FB0 and FB2. It is connected to GND for use when pin FB2 is used.
Output ON/OFF with an active-high polarity. When set to L, the current consumption is reduced to 10μA or
less.
Soft start time constant setting. The charge current is set to approx. 6.5μA and when a capacitor of 0.1μF is
connected between this pin and GND, the output rises in approx. 12ms.
Test pin for verifying the internal reference voltage. It must be set to open for actual use.
Power input. It is used with voltages ranging from 4.5V to 6V.
Inductor drive output
Power GND pin. This is the output GND. It is connected so that where at all possible, no impedance is
shared with other GND pins (GND, FB_GND).
For generating the gate voltage of the internal high-side n-channel MOS transistor. A capacitor with a
capacitance of at least 0.1μF (max. 2.2μF) is connected between this pin and the SW pin for use.
Transconductance-type Error_Amp output. An integration constant is provided between this pin and GND to
implement phase compensation.
Used to feed back the output voltage to this pin when the output voltage is to be set to 3.3V. In such a case,
FB_GND is connected to GND. Refer to application circuit 1.
When the output voltage is to be set to a desired value, connect resistors between FB0 and GND and
between FB0 and VOUT to feed back the output voltage to this pin. In such a case, leave FB_GND and
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