DATASHEET
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
Description
The MK1716-01 is a versatile serial programmable clock
source which takes up very little board space.
The device can simultaneously generate two groups of 4
output clocks and a reference clock output. Both clock
groups (CLKA and CLKB) are derived from a single PLL,
and have the ability to incorporate Spread Spectrum
frequency modulation for reduced system EMI. Each group
has control of independent PLL output divide values.
Outputs may be programmed on the fly, and will lock to a
new frequency in 10 ms or less.
Each of the two groups are powered by a separate VDDIO
voltage. The reference clock uses the fixed VDD voltage.
VDDIO may vary from 2.5 V to VDD.
The devices includes a OE pin which tri-states the output
clocks and when tied low.
IDT’s VersaClock
TM
software allows the user to generate
MK1716-01 device optimizing configuration code for target
output frequencies and spread spectrum amounts.
MK1716-01
Features
•
Packaged in 28-pin SSOP
•
Operating voltage 3.3 V
•
Serially programmable: user determines the output
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•
•
•
•
•
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frequency via a 3-wire interface
Highly accurate frequency generation
M/N Multiplier PLL: M = 1..2048, N = 1..1024
Eliminates the need for custom Quartz Oscillators
Input crystal frequency of 5-27 MHz
Input clock frequency of 3-50 MHz
Output clock frequencies of 250 kHz to 133.33 MHz
Spread Spectrum frequency modulation for reduced
system EMI
Center or down spread ±0.5% min to 4% total
Selectable 32 kHz and 120 kHz modulation rate
Advanced, low power, sub-micron CMOS process
Separate VDD ‘s for each bank of 4 outputs
Output skew <250 ps within output bank
OE control on outputs
Block Diagram
VDD
4
VDDIOA
STROBE
SCLK
DATA
PLL
with
Spread
SpectrumCircuit
DIV A
4
CLKA
VDDIOB
DIV B
4
CLKB
Crystal or
clock input
X1/ICLK
X2
External capacitors are
required with a crystal input.
Clock
Buffer/
Crystal
Ocsillator
6
GND
REF OUT
OE
IDT™
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
1
MK1716-01
REV H 051310
MK1716-01
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
SSCG
Pin Assignment
DATA
X2
X1/ICLK
REFOUT
VDD
VDD
GND
GND
GND
CLKA
CLKA
CLKA
CLKA
VDDIOA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
STROBE
SCLK
OE
VDD
VDD
VDD
GND
GND
CLKB
CLKB
CLKB
CLKB
VDDIOB
Note:
Clock A and Clock B can be at the same frequency or not,
but must be powered by separate VDDs.
Pin Descriptions
Pin
Number
1
2
3
4
5-6
7-9
10-13
14
15
16-19
20-21
22-24
25
26
27
28
Pin
Name
DATA
X2
X1/ICLK
REFOUT
VDD
GND
CLKA
VDDIOA
VDDIOB
CLKB
GND
VDD
OE
SRCLK
STROBE
GND
Pin
Type
Input
XO
XI
Output
P
P
Output
P
P
Output
P
P
Input
Input
Input
Input
Pin Description
Serial shift register data input.
Connect to crystal. Leave open for clock input.
Connect this pin to a crystal or external clock input.
Reference clock output.
Connect to +3.3 V.
Connect to ground.
Output clock.
Power supply to CLKA.
Power supply to CLKB.
Output clock.
Connect to ground.
Connect to +3.3 V.
Output enable active high.
Serial shift register clock.
Strobe to load data. See timing diagram. Use external 250 kOhm
pull-up.
Connect to ground.
IDT™
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
2
MK1716-01
REV H 051310
MK1716-01
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
SSCG
Configuring the MK1716-01
Initial State: The MK1716-01 may be configured to have up to nine frequency outputs, utilizing a single PLL and
on-board spread spectrum circuitry. Unprogrammed, the part has the following outputs, related to the reference
input clock:
Default Outputs
Output
Clock 1-9 (Pins 4, 10 - 19)
Frequency
Reference output
The STROBE pin must have an external 250 kOhm pull-up resistor to acheive the Initial State.
The input crystal range for the MK1716-01 is 5 MHz to 27 MHz.
The MK1716-01 can be programmed to set the output functions and frequencies. 160 data bits generated by the
VersaClock
TM
software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the MK1716-01, taking STROBE high will send this data
to the internal latch and the CLK output will lock within 10 ms.
Note:
STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high state and
SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will change accordingly.
Although this will not damage the MK1716-01, it is recommended that STROBE be kept low while DATA is being
clocked into the MK1716-01 in order to avoid unintended changes on the output clocks.
AC Parameters for Writing to the MK1716-01
Parameter
t
SETUP
t
HOLD
t
W
t
S
Condition
Setup time
Hold time after SCLK
Data wait time
Strobe pulse width
SCLK Frequency
Min.
10
10
10
40
Max.
Units
ns
ns
ns
ns
30
MHz
DATA
t
setup
Bit160
Bit159
Bit158
t
hold
Bit3
Bit2
Bit1
SCLK
t
w
STROBE
t
s
Figure 2. Tim ing Diagram for Program m ing the M K1716-01
IDT™
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
3
MK1716-01
REV H 051310
MK1716-01
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
SSCG
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to each clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers.
STROBE Pull-up Resistor
In order for the device to start up in the default state, a 250
kOhm pull-up resistor is required.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
MK1716-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
MK1716-01 Configuration Capabilities
The architecture of the MK1716-01 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The MK1716-01 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from the
same PLL.
Each output frequency can be represented as:
Output Freq. = (Ref. Freq)*(M/N)/Output Divide
Each output clock bank has an separate voltage drive
control pin (VDDIOA and VDDIOB) that sets the output
clock voltage swing.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
IDT™
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
4
MK1716-01
REV H 051310
MK1716-01
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
SSCG
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
is the target frequency. The effective average frequency is
less than the target frequency.
The MK1716-01 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between ±0.125% to ±2.0%. For down spread,
the frequency can be modulated between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Spread Spectrum Modulation
The MK1716-01 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By modulating
the output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electro-magnetic interference (EMI).
The modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1716-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD + 0.5
VDD + 0.5
150
260
Units
V
V
V
°
C
°
C
IDT™
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
5
MK1716-01
REV H 051310
嵌入式系统
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