DATA BULLETIN
MX803A
Features
•
Full Duplex Audio Signaling Processor
Single Tone
Selective Call systems
•
Tone Decoder with programmable
NOTONE timer.
•
Two Individual tone encoders and a
programmable TX Period Timer.
•
Low Power CMOS Device
•
On-Chip programmable amplifier.
•
C-BUS Compatible
SIGNAL INPUT BIAS
DIGITAL
NOISE
FILTER 1
RX FILTER
SWITCH
Audio Signaling Processor
PRELIMINARY INFORMATION
Applications
•
Signaling Systems supported
SelCall (CCIR, EEA, ZVEI I / II /III)
2-Tone SelCall
DTMF Encode
•
Inband Tone Signaling capability for
LMR and other Radio Systems.
(RX)
AUDIO IN
DIGITAL
NOISE
FILTER 2
COMMAND DATA
QUALITY
METER
PROGRAMMABLE
NOTONE
TIMER
REPLY DATA
GATE TIME
GENERATOR
C-BUS
INTERFACE
AND
CONTROL
LOGIC
CHIP SELECT
INTERRUPT
SERIAL CLOCK
LOGIC INPUT
FREQUENCY
COUNTER
V
DD
PROGRAMMABLE
(TX PERIOD)
TIMER
V
BIAS
TONE 1
GENERATOR
5-/2-TONE
DTMF 1
LOW
PASS
FILTER
TONE 1 OUT
SUM IN
SWITCHED SUM OUT
V
SS
_
V
BIAS
XTAL/
CLOCK
XTAL
AUDIO SWITCH IN
AUDIO
SWITCH
SUMMING
SWITCH
SUM OUT
CAL/CUES OUT
+
SUMMING
AMPLIFIER
CUES
CAL/CUES
SWITCH
CLOCK
GENERATOR
CAL
TONE 2
GENERATOR
CUES/DTMF 2
LOW
PASS
FILTER
TONE 2 OUT
SWITCH OUT
The MX803A is an audio signaling processor that provides inband tone signaling capabilities for LMR and other Radio
systems. A low-power CMOS device, the MX803A is a member of the DBS800 (Digitally integrated Baseband Sub-
system) IC family (See section 4.2). Supported Signaling systems include SelCall (CCIR, EEA, ZVEI I, II, and III) 2-Tone
SelCall and DTMF encode. The use of a non-predictive decoder and a versatile encoder, allows the MX803A to operate
in any standard or non-standard tone system.
The MX803A is a full-duplex device for use with Single Tone or Selective Call systems. The MX803A consists of a tone
decoder with a programmable NOTONE timer, two individual tone encoders and a programmable TX period timer, and an
on-chip summing amplifier. Under the control of a
µC,
the MX803A will simultaneously encode and transmit 1 or 2 audio
tones in the 208-3000Hz range, as well as detect, decode, and indicate the frequency of any non-predicted input tone in
the frequency range of 313 to 6000Hz.
The MX803A is available in 24-pin CDIP (MX803AJ), 24-pin PLCC (MX803ALH), and 24-pin SOIC (MX803ADW)
packages.
©
1996 MX•COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
Audio Signaling Processor
2
MX803A PRELIMINARY INFORMATION
CONTENTS
Section
Page
1. Block Diagram .................................................................................................................................. 3
2. Signal List ......................................................................................................................................... 4
3. External Components ...................................................................................................................... 6
4. General Description ......................................................................................................................... 7
4.1 DESCRIPTION.......................................................................................................................................... 7
4.2 DBS800 Systems ...................................................................................................................................... 7
4.3 C-BUS Control .......................................................................................................................................... 8
5. Application ....................................................................................................................................... 8
5.1 MX803A Internal Registers ....................................................................................................................... 8
5.2 Address/Commands.................................................................................................................................. 9
5.3 Powersave ............................................................................................................................................... 18
5.4 Interrupt Request
IRQ
.............................................................................................................................. 19
5.5 Operational Recommendations................................................................................................................ 19
5.6 General Reset .......................................................................................................................................... 20
6. Timing Information.......................................................................................................................... 20
7. Performance Specification............................................................................................................. 22
7.1 Electrical Performance ............................................................................................................................. 22
7.2 Packaging ................................................................................................................................................ 25
MX•COM, Inc. reserves the right to change specifications at any time and without notice.
©
1996 MX•COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
Audio Signaling Processor
3
MX803A PRELIMINARY INFORMATION
1. Block Diagram
SIGNAL INPUT BIAS
DIGITAL
NOISE
FILTER 1
RX FILTER
SWITCH
(RX)
AUDIO IN
DIGITAL
NOISE
FILTER 2
COMMAND DATA
QUALITY
METER
PROGRAMMABLE
NOTONE
TIMER
REPLY DATA
GATE TIME
GENERATOR
C-BUS
INTERFACE
AND
CONTROL
LOGIC
CHIP SELECT
INTERRUPT
SERIAL CLOCK
LOGIC INPUT
FREQUENCY
COUNTER
V
DD
PROGRAMMABLE
(TX PERIOD)
TIMER
V
BIAS
TONE 1
GENERATOR
5-/2-TONE
DTMF 1
LOW
PASS
FILTER
TONE 1 OUT
SUM IN
SWITCHED SUM OUT
V
SS
_
V
BIAS
XTAL/
CLOCK
XTAL
AUDIO SWITCH IN
AUDIO
SWITCH
SUMMING
SWITCH
SUM OUT
CAL/CUES OUT
+
SUMMING
AMPLIFIER
CUES
CAL/CUES
SWITCH
CLOCK
GENERATOR
CAL
TONE 2
GENERATOR
CUES/DTMF 2
LOW
PASS
FILTER
TONE 2 OUT
SWITCH OUT
Figure 1: Block Diagram
©
1996 MX•COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
Audio Signaling Processor
4
MX803A PRELIMINARY INFORMATION
2. Signal List
Pin No.
1
2
3
Name
XTAL
Type
Description
Output Output of the on-chip clock oscillator. External components are required at this
output when a Xtal is used. See Figure 2.
Input
Input to the on-chip clock oscillator inverter. A Xtal or externally derived clock
should be connected here. See Figure 2.
Xtal/Clock
Reply Data
Output C-BUS serial data output to the
µC.
The transmission of Reply Data bytes is
synchronized to the Serial Clock under the control of the Chip Select input.
This 3-state output is held at high impedance when not sending data to the
µC.
See Figure 8 and Figure 9.
Input
C-BUS data loading control function. This input is provided by the
µC.
Data
transfer sequences are initiated, completed or aborted by the chip select signal.
See Figure 8 and Figure 9.
C-BUS serial data input from the
µC.
Data is loaded to this device in 8-bit
bytes, MSB (B7) first and LSB (B0) last, synchronized to the Serial Clock. See
Figure 8 and Figure 9.
This “real-time” input is available as a general purpose logic input port which
can be read from the Status Register. See Table 3.
G/Purpose Timer Period Expired
NOTONE Timer Period Expired
RX Tone Measurement Complete
These interrupts are inactive during relevant powersave conditions and can be
disabled by bits 5 and 6 in the Control Register.
4
CS
5
Command Data
Input
6
Logic Input
Input
7
IRQ
Output Output of this pin indicates an interrupt condition to the
µC
by going to a logic
“0.” This is a “wire-or-able” output, allowing the connection of up to 8
peripherals to 1 interrupt port on the
µC.
This pin has a low impedance
pulldown to logic “0” when active and a high impedance when inactive. The
system IRQ line requires one pullup resistor to V
DD
. The conditions that cause
interrupts are indicated in the Status Register and are shown below:
Input
Input to the stand-alone on-chip Audio Switch. This function is
enabled/disabled by Bit 7 of the Control Register
Negative supply (GND).
Received audio tone signaling input. This input must be ac coupled and
connected, using external components, to the Signal Input Bias pin. See Figure
2.
External components are required between this input and the RX Audio In pin.
See Figure 2.
10
11
12
13
Audio Switch In
Audio Switch Out
V
SS
Rx Audio In
Output Output of the stand-alone on-chip Audio Switch..
Power
Input
14
15
16
Signal Input Bias
V
BIAS
Tone 1 Out
Input
Output Internal circuitry bias signal, held at V
DD
/2. This pin should be decoupled to V
SS
by capacitor C2. See Figure 2..
Output Tone 1 Generator (2-/5-tone Selcall or DTMF 1) output. External gain and
coupling components are required at this output when operating in a complete
DBS 800 audio installation. The frequency of this output is determined by
writing to the TX Tone Generator 1 Register (Table 5). See Figure 2.
Output Tone 2 Generator (2-/5-tone Selcall, CUES or DTMF 2) output. External gain
and coupling components are required at this output when operating in a
complete DBS 800 audio installation. The frequency of this output is
determined by writing to the TX Tone Generator 2 Register (Table 5).
See Figure 2.
17
Tone 2 Out
©
1996 MX•COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
Audio Signaling Processor
5
MX803A PRELIMINARY INFORMATION
Pin No.
18
Name
CAL/CUES Out
Type
Description
Output An auxiliary, selectable tone frequency output, providing a square wave
CALibration signal from the Tone 2 Generator or a sine wave CUES (beep)
signal from the Summing Amplifier. The output mode (CAL or CUES) is
selected by Bit 14 in the TX Tone Generator 2 Register (Table 5). When Tone
Generator 2 is set to Notone, the CAL input is pulled to V
BIAS
; during a
powersave of Tone Generator 2 it is held at V
SS
.
Input
Input to the on-chip Summing Amplifier. This amplifier is available for
combining Tone 1 and Tone 2 outputs (DTMF). Gain and coupling components
should be used at this input to provide the required system gains. See Figure 2
and Figure 3
19
Sum in
20
21
Sum Out
Switched Sum
Out
Serial Clock
Output Output of the on-chip summing amplifier. Combined tones (1 and 2) are
available at this output. See Figure 2 and Figure 3.
Output This is the combined tone output available for transmitter modulation. The
switch allows control of the MX803A output. Control of this switch is by Bit 4 of
the Control Register. See Figure 2 and Figure 3.
Input
C-BUS serial clock input. This clock, produced by the
µC,
is used for transfer
timing of commands and data to and from the MX803A. See Figure 8 and
Figure 9.
Positive supply. A single +5 volt power supply is required. Levels and voltages
within this Audio Signaling Processor are dependent upon this supply..
No Internal Connection. These pins may be connected to V
SS
to improve
screening and reduce noise levels around the MX803A.
23
24
8, 9, 22
V
DD
N/C
Power
©
1996 MX•COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
