HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT7007S/L
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
Low-power operation
– IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
IDT7007 easily expands data bus width to 16 bits or more
◆
◆
◆
◆
◆
◆
◆
◆
◆
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA and PLCC and a 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
14L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
A
14R
A
0R
(1,2)
Address
Decoder
15
MEMORY
ARRAY
15
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2940 drw 01
JANUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC 2940/12
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very LOW standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 850mW of power.
The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC,
and an 80-pin thin quad flatpack, TQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-PRF-38535
QML, Class B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Pin Configurations
(1,2,3)
I/O
1L
I/O
0L
N/C
OE
L
R/
W
L
SEM
L
CE
L
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
11/06/01
9
8
7
6
5
4
3
IDT7007J
J68-1
(4)
68-Pin PLCC
Top View
(5)
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
0R
A
1R
A
2R
A
3R
A
4R
2940 drw 02
OE
R
R/
W
R
SEM
R
CE
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
I/O
7R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
2
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
INDEX
N/C
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
N/C
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
11/06/01
7007PF
PN80-1
(4)
80-Pin TQFP
Top View
(5)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
,
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
2940 drw 03
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
N/C
N/C
3
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/S
40
38
INT
R
A
1R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
28
A
11R
26
GND
11/06/01
10
45
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
34
A
5R
33
A
6R
31
A
8R
29
A
10R
27
A
12R
09
08
56
57
A
11L
A
10L
58
59
V
CC
A
12L
61
60
A
13L
07
IDT7007G
G68-1
(4)
68-Pin PGA
Top View
(5)
06
A
14L
62
63
05
SEM
L
CE
L
64
65
04
OE
L
R/W
L
03
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
01
A
INDEX
NOTES:
1. All Vcc pins must be connected to power supply
2. All GND pins must be connected to ground.
3. Package body is approximately 1.8 in x 1.8 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
25
24
A
14R
A
13R
23
22
SEM
R
CE
R
20
OE
R
21
R/W
R
,
02
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
E
F
G
H
J
18
19
I/O
7R
N/C
17
I/O
6R
K
4
I/O
3L
I/O
5L
B
C
L
2940 drw 04
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2940 tbl 01
4
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
2940 tbl 02
Mode
NOTE:
1. A
0L
— A
14L
≠
A
0R
— A
14R
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
H
L
R/W
H
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
______
Mode
Read Semaphore Flag Data Out (I/O
0
-I/O
7
)
Write I/O
0
into Semaphore Flag
Not Allowed
2940 tbl 03
↑
X
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's. These eight semaphores are addressed by A
0
- A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Military
Ambient
Temperature
-55
O
C to+125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
2940 tbl 05
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
Commercial
Industrial
o
mA
2940 tbl 04
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sec-tions of this specification is not implied. Exposure
to absolute maxi-mum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2940 tbl 06
Capacitance
(T
A
= +25°C, f = 1.0Mhz)
Symbol
C
IN
C
OUT
Parameter
(1)
____
Conditions
(2)
Max.
9
10
Unit
pF
pF
2940 tbl 07
Input Capacitance
Output Capacitance
V
IN
= 3dV
V
OUT
= 3dV
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested. TQFP package only.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
