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74LVX244SJX_NL

产品描述Bus Driver, 2-Func, 4-Bit, True Output, CMOS, PDSO20,
产品类别逻辑    逻辑   
文件大小85KB,共6页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
标准
下载文档 详细参数 全文预览

74LVX244SJX_NL概述

Bus Driver, 2-Func, 4-Bit, True Output, CMOS, PDSO20,

74LVX244SJX_NL规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Fairchild
Reach Compliance Codecompliant
控制类型ENABLE LOW
JESD-30 代码R-PDSO-G20
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.004 A
位数4
功能数量2
端子数量20
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP20,.3
封装形状RECTANGULAR
封装形式SMALL OUTLINE
包装方法TAPE AND REEL
电源3.3 V
Prop。Delay @ Nom-Sup12 ns
认证状态Not Qualified
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
Base Number Matches1

文档预览

下载PDF文档
74LVX244 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
February 1993
Revised April 2005
74LVX244
Low Voltage Octal Buffer/Line Driver with
3-STATE Outputs
General Description
The LVX244 is an octal non-inverting buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density. The inputs tolerate up
to 7V allowing interface of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX244M
74LVX244SJ
74LVX244MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Inputs
OE
1
L
I
n
L
H
X
Inputs
OE
2
L
L
H
H
X
HIGH Voltage Level
Immaterial
Outputs
(Pins 12, 14, 16, 18)
L
H
Z
Outputs
I
n
L
H
X
(Pins 3, 5, 7, 9)
L
H
Z
L LOW Voltage Level
Z High Impedance
Connection Diagram
L
H
© 2005 Fairchild Semiconductor Corporation
DS011552
www.fairchildsemi.com

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