DISCRETE SEMICONDUCTORS
DATA SHEET
BF1105; BF1105R; BF1105WR
N-channel dual-gate MOS-FETs
Product specification
Supersedes data of 1997 Dec 01
File under Discrete Semiconductors, SC07
1997 Dec 02
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
FEATURES
•
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
•
Low noise gain controlled amplifier
up to 1 GHz.
•
Internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
APPLICATIONS
•
VHF and UHF applications with 5 V
supply voltage, such as television
tuners and professional
communications equipment.
page
BF1105; BF1105R; BF1105WR
PINNING
PIN
1
2
3
4
DESCRIPTION
source
drain
gate 2
gate 1
Top view
MSB035
handbook, 2 columns
3
4
2
1
BF1105R marking code:
NAp.
Fig.2
Simplified outline
(SOT143R).
4
3
alfpage
3
4
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1105,
BF1105R and BF1105WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
y
fs
C
ig1-ss
C
rss
F
X
mod
T
j
PARAMETER
drain-source voltage
drain current
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
cross-modulation
operating junction temperature
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
f = 1 MHz
f = 800 MHz
T
amb
≤
80
°C
CONDITIONS
MIN.
−
−
−
25
−
−
−
−
TYP.
−
−
−
31
2.2
25
1.7
−
−
MAX.
7
30
200
−
2.7
40
2.5
−
150
UNIT
V
mA
mW
mS
pF
fF
dB
dBµV
°C
1
Top view
2
MSB014
2
Top view
1
MSB842
BF1105 marking code:
NEp.
BF1105WR marking code:
NA.
Fig.1
Simplified outline
(SOT143B).
Fig.3
Simplified outline
(SOT343R).
input level for k = 1% at 40 dB AGC 100
1997 Dec 02
2
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation
storage temperature
operating junction temperature
BF1105; BF1105R; BF1105WR
CONDITIONS
−
−
−
−
T
amb
≤
80
°C;
note 1; see Fig.4
−
MIN.
7
MAX.
V
30
±10
±10
200
+150
+150
UNIT
mA
mA
mA
mW
°C
°C
−65
−
MGM243
handbook, halfpage
250
Ptot
(mW)
200
150
100
50
0
0
40
80
120
160
Tamb (°C)
Fig.4 Power derating curve.
1997 Dec 02
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
R
th j-s
Note
1. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
PARAMETER
drain-source breakdown voltage
PARAMETER
thermal resistance from junction to ambient in free air
thermal resistance from junction to soldering point
BF1105; BF1105R; BF1105WR
CONDITIONS
note 1
VALUE
350
200
UNIT
K/W
K/W
CONDITIONS
V
G1-S
= V
G2-S
= 0; I
D
= 10
µA
MIN.
7
7
7
0.3
8
−
−
TYP.
−
−
−
0.8
−
−
−
MAX.
−
−
−
1.2
16
50
20
UNIT
V
V
V
V
mA
nA
nA
V
(BR)G1-SS
gate 1-source breakdown voltage V
G2-S
= 0; I
D
= 0; I
G1-S
= 10
µA
V
(BR)G2-SS
gate 2-source breakdown voltage V
G1-S
= V
DS
= 0; I
G2-S
= 10
µA
V
G2-S (th)
I
DSX
I
G1-SS
I
G2-SS
gate 2-source threshold voltage
self-biasing drain current
gate 1 cut-off current
gate 2 cut-off current
V
G1-S
= 5 V; V
DS
= 5 V; I
D
= 20
µA
V
G2-S
= 4 V; V
DS
= 5 V
V
G1-S
= 5 V; V
G2-S
= 0; I
D
= 0
V
G1-S
= V
DS
= 0; V
G2-S
= 4 V
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
°C;
V
G2-S
= 4 V; V
DS
= 5 V; self-biasing current; unless otherwise specified.
SYMBOL
y
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F
G
p
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
noise figure
power gain
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 800 MHz; Y
S
= Y
S opt
G
S
= 2 mS; B
S
= B
S opt
; G
L
= 0.5 mS;
B
L
= B
L opt
; f = 200 MHz; see Fig.16
G
S
= 3.3 mS; B
S
= B
S opt
; G
L
= 1 mS;
B
L
= B
L opt
; f = 800 MHz; see Fig.17
X
mod
cross-modulation
input level for k = 1% at 0 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; see Fig.18
input level for k = 1% at 40 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; see Fig.18
CONDITIONS
pulsed; T
j
= 25
°C
MIN.
25
−
−
−
−
−
−
−
85
100
TYP.
31
2.2
1.6
1.2
25
1.7
38
20
−
−
MAX.
−
2.7
−
−
40
2.5
−
−
−
−
UNIT
mS
pF
pF
pF
fF
dB
dB
dB
dBµV
dBµV
reverse transfer capacitance f = 1 MHz
1997 Dec 02
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
handbook, halfpage
25
MGM244
ID
VG1 = 1.7 V
handbook, halfpage
40
MGM245
(mA)
20
1.6 V
1.5 V
15
1.4 V
10
1.3 V
ID
(mA)
30
VG2-S = 4 V
3.5 V
3V
2.5 V
20
2V
1.2 V
5
1.1 V
1.5 V
1V
0
0
2
4
6
VDS (V)
8
0
0
0.5
1
1.5
2
1V
2.5
VG1 (V)
10
V
G2-S
= 4 V.
T
j
= 25
°C.
V
DS
= 5 V.
T
j
= 25
°C.
Fig.5 Output characteristics; typical values.
Fig.6 Transfer characteristics; typical values.
MGM246
handbook, halfpage
40
handbook, halfpage
16
MGM247
yfs
(mS)
30
VG2-S = 4 V
3.5 V
ID
(mA)
12
(1) (2)
(3)
3V
20
8
(4) (5)
10
4
2V
0
0
10
20
2.5 V
0
ID (mA)
30
0
1
2
3
4
5
VG2-S (V)
V
DS
= 5 V.
T
j
= 25
°C.
(1) V
DS
= 5 V.
(2) V
DS
= 4.5 V.
(3) V
DS
= 4 V.
(4) V
DS
= 3.5 V.
(5) V
DS
= 3 V.
Fig.7
Forward transfer admittance as a function
of drain current; typical values.
Fig.8
Drain current as a function of gate 2
voltage; typical values.
1997 Dec 02
5
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