Crystal or Differential to LVCMOS/
LVTTL Clock Buffer
General Description
The IDT8L3010I is a low skew, 1-to-10 LVCMOS / LVTTL Fanout
Buffer. The low impedance LVCMOS/LVTTL outputs are designed to
drive 50 series or parallel terminated transmission lines.
The IDT8L3010I is characterized at full 3.3V and 2.5V, mixed
3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output
operating supply modes. The input clock is selected from two
differential clock inputs or a crystal input. The differential input can
be wired to accept a single-ended input. The internal oscillator circuit
is automatically disabled if the crystal input is not selected.
IDT8L3010I
DATA SHEET
Features
•
•
•
•
•
•
•
•
Ten LVCMOS / LVTTL outputs up to 200MHz
Differential input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Output skew: 50ps (maximum) @ 3.3V/3.3V
Additive RMS phase jitter: 0.24ps (typical) @ 3.3V/3.3V
Synchronous output enable to avoid clock glitch
Power supply modes:
Core / Output
3.3V / 3.3V
2.5V / 2.5V
3.3V / 2.5V
3.3V / 1.8V
3.3V / 1.5V
2.5V / 1.8V
2.5V / 1.5V
5V input tolerance
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
•
•
•
Block Diagram
Q0
Pulldown
Pin Assignment
Q9
VDDO
Q8
GNDO
Q7
VDDO
Q6
Q5
24 23 22 21 20 19 18 17
Q2
SEL[1: 0]
Q1
GNDO
GND
nCLK1
CLK1
SEL1
SEL0
OE
GNDO
25
26
16
15
GNDO
GND
nCLK0
CLK0
XTAL_OUT
XTAL_IN
VDD
GNDO
CLK0
nCLK0
Pulldown
Pullup Pulldown
/
00
Q3
CLK1
nCLK1
Pulldown
Pullup/Pulldown
Q4
01
Q5
IDT8L3010I
27
14
32 Lead VFQFN
28
5mm x 5mm 0.925mm
13
package body
29
12
NL Package
30
11
Top View
31
32
1
2
3
4
5
6
7
8
10
9
XTAL_OUT
XTAL_IN
OSC
1x
Q6
Q8
Q9
OE
Pulldown
SYNC
.
IDT8L3010ANLGI REVISION A JANUARY 12, 2012
1
Q0
VDDO
Q1
GNDO
Q2
VDDO
Q3
Q4
©2012 Integrated Device Technology, Inc.
Q7
IDT8L3010I Data Sheet
CRYSTAL OR DIFFERNTIALTO LVCMOS/LVTTL CLOCK BUFFER
Table 1. Pin Descriptions
Number
1, 3, 5, 7, 8,
17, 18, 20, 22, 24
2, 6, 19, 23
4, 9, 16,
21, 25, 32
15, 26
10
11,
12
13
14
27
28
29, 30
31
Name
Q0, Q1, Q2, Q3, Q4
Q5, Q6, Q7, Q8, Q9
V
DDO
GNDO
GND
V
DD
XTAL_IN,
XTAL_OUT
CLK0
nCLK0
nCLK1
CLK1
SEL1, SEL0
OE
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins.
Power supply output ground.
Power supply core ground.
Power supply pin.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Non-inverting differential clock.
Inverting differential clock. Internal resistor bias to V
DD
/2.
Inverting differential clock. Internal resistor bias to V
DD
/2.
Non-inverting differential clock.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable. LVCMOS/LVTTL interface levels. See Table 3B.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
V
DDO
= 3.465V
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 2.625V
V
DDO
= 2V
V
DDO
= 1.65V
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
V
DDO
= 1.5V ± 0.15V
Test Conditions
Minimum
Typical
4
51
51
13
12
10
9
14
17
30
55
Maximum
Units
pF
k
k
pF
pF
pF
pF
IDT8L3010ANLGI REVISION A JANUARY 12, 2012
2
©2012 Integrated Device Technology, Inc.
IDT8L3010I Data Sheet
CRYSTAL OR DIFFERNTIALTO LVCMOS/LVTTL CLOCK BUFFER
Function Tables
Table 3A. SELx Function Table
Control Input
SEL[1:0]
00 (default)
01
11 or 10
Selected Input Clock
CLK0, nCLK0
CLK1, nCLK1
XTAL
Table 3B. OE Function Table
Control Input
OE
0 (default)
1
Function
Q[0:9]
High-Impedance
Enabled
Table 3C. Input/Output Operation Table
Input State
OE
0
1
SEL[1:0]
X
10 or 11
CLK[0:1], nCLK[0:1]
Do Not Care
Do Not Care
CLK0=nCLK0 =Open
CLK0=nCLK0 =Ground
1
00
CLK0 = HIGH, nCLK0 = LOW
CLK0 = LOW, nCLK0 = HIGH
CLK1=nCLK1 =Open
CLK1=nCLK1 =Ground
1
01
CLK1 = HIGH, nCLK1 = LOW
CLK1 = LOW, nCLK1 = HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
Output State
Q[0:9]
High-Impedance
Active
LOW
LOW
CLKx/
nCLKx
OE
Q[0:9]
High Impedance
tDIS
tEN
Figure 1. OE Timing Diagram
NOTE: The outputs will enable or disable following 2 to 3 clock cycles after the transition on the OE input.
IDT8L3010ANLGI REVISION A JANUARY 12, 2012
3
©2012 Integrated Device Technology, Inc.
IDT8L3010I Data Sheet
CRYSTAL OR DIFFERNTIALTO LVCMOS/LVTTL CLOCK BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
CLK
X,
nCLK
X,
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 5V
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
33.1°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V±5%, V
DDO
= 3.3V±5% or 2.5V±5% or 1.8V±0.2V or 1.5V±0.15V,
T
A
= -40°C to 85°C
Symbol
V
DD
Parameter
Power Supply Voltage
Test Conditions
Minimum
3.135
3.135
2.375
V
DDO
Output Supply Voltage
1.6
1.35
I
DD
Power Supply Current
OE = 0
OE = 1, V
DDO
= 3.3V±5%, Outputs Unloaded
I
DDO
Output Supply Current
OE = 1, V
DDO
= 2.5V±5%, Outputs Unloaded
OE = 1, V
DDO
= 1.8V±0.2V, Outputs Unloaded
OE = 1, V
DDO
= 1.5V±0.15V, Outputs Unloaded
1.8
1.5
2
1.65
38
5
5
5
5
V
V
mA
mA
mA
mA
mA
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
Units
V
V
V
IDT8L3010ANLGI REVISION A JANUARY 12, 2012
4
©2012 Integrated Device Technology, Inc.
IDT8L3010I Data Sheet
CRYSTAL OR DIFFERNTIALTO LVCMOS/LVTTL CLOCK BUFFER
Table 4B. Power Supply DC Characteristics, V
DD
= 2.5V±5%, V
DDO
= 2.5V±5% or 1.8V±0.2V or 1.5V±0.15V,
T
A
= -40°C to 85°C
Symbol
V
DD
Parameter
Power Supply Voltage
Test Conditions
Minimum
2.375
2.375
V
DDO
Output Supply Current
1.6
1.35
I
DD
Power Supply Current
OE = 0
OE = 1, V
DDO
= 2.5V±5%, Outputs Unloaded
I
DDO
Output Supply Current
OE = 1, V
DDO
= 1.8V±0.2V, Outputs Unloaded
OE = 1, V
DDO
= 1.5V±0.15V, Outputs Unloaded
Typical
2.5
2.5
1.8
1.5
Maximum
2.625
2.625
2
1.65
38
5
5
5
Units
V
V
V
V
mA
mA
mA
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
Input Low Voltage
Input High Current
Input Low Current
OE, SEL[1:0]
OE, SEL[1:0]
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V±5%
V
OH
Output High Voltage; NOTE 1
V
DDO
= 2.5V±5%
V
DDO
= 1.8V±0.2V
V
DDO
= 1.5V±0.15V
V
DDO
= 3.3V±5% or 2.5V±5%
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 1.8V±0.2V
V
DDO
= 1.5V±0.15V
-5
2.6
1.8
1.2
0.97
0.5
0.4
0.37
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
V
V
V
V
V
V
V
IL
I
IH
I
IL
NOTE 1: Outputs terminated with 50 to V
DDO
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
IDT8L3010ANLGI REVISION A JANUARY 12, 2012
5
©2012 Integrated Device Technology, Inc.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
