74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 6 — 20 November 2012
Product data sheet
1. General description
The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and
outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data
enable input (E) is LOW. The state of each D input, one set-up time before the
LOW to HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. Input E must be stable only one set-up time prior to the LOW to HIGH transition
for predictable operation.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50
transmission lines at 125
C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC377D
74LVC377DB
74LVC377PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
4. Functional diagram
11
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
E
1
mna918
1C2
G1
1
2
5
6
9
12
15
16
19
13
14
17
18
3
4
7
8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2D
2
5
6
9
12
15
16
19
mna919
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
5. Pinning information
5.1 Pinning
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
377
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
mna917
GND 10
Fig 3.
Pin configuration SO20 and (T)SSOP20
5.2 Pin description
Table 2.
Symbol
E
CP
D[0:7]
Pin description
Pin
1
11
3, 4, 7, 8, 13, 14, 17, 18
Description
data enable input (active LOW)
clock input (LOW to HIGH; edge-triggered)
data input
74LVC377_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 06 — 20 November 2012
2 of 15
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Table 2.
Symbol
Q[0:7]
GND
V
CC
Pin description
?ontinued
Pin
2, 5, 6, 9, 12, 15, 16, 19
10
20
Description
flip-flop output
ground (0 V)
power supply
6. Functional description
Table 3.
Function table
[1]
Control
CP
E
I
I
h
H
X
Input
Dn
h
I
X
X
Output
Qn
H
L
NC
NC
Operating mode
Load 1
Load 0
Hold
Do nothing
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
= LOW to HIGH CP transition
NC = no change
X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
O
I
OK
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output current
output clamping current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
[2]
Min
0.5
0.5
0.5
50
-
-
-
100
65
Max
+6.5
+5.5
V
CC
+ 0.5
-
50
50
100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
V
I
< 0 V
V
O
= 0 V to V
CC
V
O
> V
CC
or V
O
< 0 V
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
derate linearly with 5.5 mW/K.
74LVC377_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 06 — 20 November 2012
3 of 15
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
0
40
0
0
Typ
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
-
-
-
-
-
-
-
-
-
-
0.1
0.2
0.45
0.6
0.4
0.55
5
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
V
V
V
V
V
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
1.08
1.7
2.0
-
-
-
-
40 C
to +85
C
Min
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
0.12
0.7
0.8
Max
40 C
to +125
C
Min
1.08
1.7
2.0
-
-
-
-
-
-
0.12
0.7
0.8
0.65
V
CC
-
Max
V
V
V
V
V
V
V
Unit
0.65
V
CC
-
0.35
V
CC
-
0.35
V
CC
V
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND -
current
74LVC377_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 06 — 20 November 2012
4 of 15
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Table 6.
Static characteristics
?ontinued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
CC
I
CC
supply
current
additional
supply
current
input
capacitance
Conditions
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
-
5.0
-
-
-
pF
-
-
40 C
to +85
C
Min
Typ
[1]
0.1
5
10
500
Max
-
-
40 C
to +125
C
Min
40
5000
Max
A
A
Unit
C
I
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 6.
Symbol Parameter
t
pd
propagation
delay
Conditions
CP to Qn; see
Figure 4
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
t
W
pulse width
clock HIGH or LOW; see
Figure 4
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
t
su
set-up time
E to CP; see
Figure 5
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
Dn to CP; see
Figure 5
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
5.5
4.5
3.0
2.0
-
-
1.0
0.7
-
-
-
-
5.5
4.5
3.0
2.0
-
-
-
ns
ns
ns
ns
5.5
4.5
4.0
3.0
-
-
0.6
0.2
-
-
-
-
5.5
4.5
4.0
3.0
-
-
-
ns
ns
ns
ns
6.0
5.0
5.0
4.0
-
-
1.6
1.0
-
-
-
-
6.0
5.0
5.0
4.0
-
-
-
ns
ns
ns
ns
[2]
40 C
to +85
C
Min
-
2.5
1.8
1.5
1.5
Typ
[1]
15
7.4
4.4
4.3
4.0
Max
-
14.5
8.5
7.9
7.6
40 C
to +125
C
Unit
Min
-
2.5
1.8
1.5
1.5
Max
-
15.5
9.1
10.0
9.5
ns
ns
ns
ns
ns
74LVC377_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 06 — 20 November 2012
5 of 15
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