MK2049-01
Communications Clock PLL
Description
The MK2049 is a Phase-Locked Loop (PLL) based
clock synthesizer, which accepts an 8 kHz clock
input as a reference and generates T1, E1, T3, E3,
and OC3 frequencies. The device can also accept a
T1, E1, T3, or E3 input clock and provide the
same output for loop timing. All outputs are
frequency locked together and to the input. This
allows for the generation of locked clocks to an
8 kHz backplane clock, simplifying clock
distribution in communications systems.
MicroClock can customize this device for many
other different frequencies. Contact your
MicroClock representative for more details.
For a fixed input-output phase relationship, refer
to the MK2049-02, -03, or -3x. The MK2049-3x
are 3.3 V devices.
Features
• Packaged in 20 pin SOIC
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock or
Loop Timing frequencies
• Locks to 8 kHz ±100 ppm (External mode)
• Exact internal ratios eliminate the need for external
dividers
• Zero ppm synthesis error in all output clocks.
• Output clock rates include T1, E1, T3, E3, and
OC3÷8
• 5 V ±5% operation
• Offered in Commercial and Industrial temperature
versions
Block Diagram
VDD GND
4
4
FS3:0
4
Clock
Input
Reference
Crystal
External/
Loop
Timing
Mux
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
X1
Crystal
Oscillator
X2
8 kHz
CAP1
CAP2
1
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MDS 2049-01 J
MK2049-01
Communications Clock PLL
Pin Assignment
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8K
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
GND
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
Output Decoding Table – External Mode (MHz)
Input
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3
0
0
0
0
0
FS2
0
0
0
0
1
FS1
0
0
1
1
1
FS0
0
1
0
1
1
CLK1
1.544
2.048
22.368
17.184
19.44
CLK2
3.088
4.096
44.736
34.368
38.88
Crystal
12.288
12.288
12.288
12.288
12.96
Output Decoding Table – Loop Timing Mode (MHz)
Input
1.544
2.048
44.736
34.368
FS3
1
1
1
1
FS2
0
0
0
0
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
1.544
2.048
22.368
17.184
CLK2
3.088
4.096
44.736
34.368
Crystal
12.288
12.288
12.288
12.288
20 pin (300 mil) SOIC
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8K
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
GND
FS0
Type
I
O
I
P
P
P
P
O
O
O
I
I
I
P
P
LF
P
LF
P
I
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is applied to pins 2 and 3; clock input is applied to pin 13.
Description
Frequency Select 1. Determines CLK input/outputs per tables above.
Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
Connect to +5V.
Connect to +5V.
Connect to +5V.
Connect to ground.
Clock 2 output determined by status of FS3:0 per tables above.
Clock 1 output determined by status of FS3:0 per tables above. CLK2 divided by 2.
Recovered 8 kHz clock output. On External mode only.
Frequency Select 2. Determines CLK input/outputs per tables above.
Frequency Select 3. Determines CLK input/outputs per tables above.
Input clock connection. Connect to 8 kHz backplane or to Loop Timing clock.
Connect to ground.
Connect to +5V.
Connect a 0.030 µF ceramic capacitor and a 7.5 MΩ resistor in series between this pin and CAP2.
Connect to ground.
Connect a 0.030 µF ceramic capacitor and a 7.5 MΩ resistor in series between this pin and CAP1.
Connect to ground.
Frequency Select 0. Determines CLK input/outputs per tables above.
Type: I = Input, O = output, P = power supply connection, LF = loop filter connection
2
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MDS 2049-01 J
MK2049-01
Communications Clock PLL
Electrical Specifications
Parameter
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance, FS3:0
Input Frequency, External Mode
Input Crystal Frequency
Input Crystal Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Actual mean frequency error versus target
Conditions
Referenced to GND
-0.5
0
-40
-65
4.75
2
IOH=-4mA
IOH=-25mA
IOL=25mA
No Load, VDD=5.0V
Each output
VDD-0.4
2.4
0.4
20
±100
7
8.0000
12.2880
12.9600
1.5
1.5
60
0
Minimum
Typical
Maximum
7
VDD+0.5
70
85
250
150
5.25
0.8
Units
V
V
°C
°C
°C
°C
V
V
V
V
V
V
mA
mA
pF
kHz
MHz
MHz
ns
ns
%
ppm
ABSOLUTE MAXIMUM RATINGS (Note 1)
MK2049-01SI only
Max of 10 seconds
DC CHARACTERISTICS (VDD = 5 V unless noted)
AC CHARACTERISTICS (VDD = 5 V unless noted)
ICLK
X1, X2
X1, X2. Selection 0111
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
Any clock selection
40
49 to 51
0
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
3
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MDS 2049-01 J
MK2049-01
Communications Clock PLL
OPERATING MODES
The MK2049-01 has two operating modes: External and Loop Timing. Although both modes use an input
clock to generate various output clocks, there are important differences in their input requirements.
External Mode
The MK2049-01 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as
narrow as 10 ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1
and E1 inputs, the CLK1 output will be the same as the input frequency, with CLK2 at twice the input
frequency. For T3 and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the
input frequency.
FREQUENCY LOCKING TO THE INPUT
In both modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
INPUT AND OUTPUT SYNCHRONIZATION
The rising edges of CLK1 and CLK2 do not have a fixed phase alignment with the rising edge of ICLK.
Each time the device is powered-up, the phase relationship could change. Refer to one of the other
MK2049 versions (e.g., MK2049-02, -03, -34) if input-output phase alignment is important in your
application.
4
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MDS 2049-01 J
MK2049-01
Communications Clock PLL
LAYOUT AND EXTERNAL COMPONENTS
The MK2049-01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4
and 7, 15 and 17), and 33
Ω
series terminating resistors should be used on clock outputs with traces longer
than 1 inch (assuming 50
Ω
traces). The loop filter components should be connected as close to the chip as
possible. Refer to the next section for more information.
PC Board Layout
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as
possible and the two capacitors and resistor must be mounted next to the device as shown below. The
capacitor shown between pins 15 and 17, and the one between pins 5 and 7 are the power supply decoupling
capacitors. The high frequency output clocks on pins 8 and 9 should have a series termination of 33
Ω
connected close to the pin. Additional improvements will come from keeping all components on the same
side of the board, minimizing vias through other signal layers, and routing other signals away from the
MK2049. You may also refer to MAN05 for additional suggestions on layout of the crystal section.
The crystal traces should include pads for small capacitors from X1 and X2 to ground; these are used to
adjust the stray capacitance of the board to match the crystal load capacitance. The typical telecom reference
frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board
capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the
adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature,
and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout,
using the procedure described later in this section, titled “Determining the Crystal Frequency Adjustment
Capacitors”.
cap
Optional;
see text
Cutout in ground and power plane.
Route all traces away from this area.
G
cap
V
cap
resist.
resist.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
resist.
G
cap
cap
cap
V
V
=connect to VDD
G
=connect to GND
Figure 1. MK2049-01 Layout Example
5
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MDS 2049-01 J
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