MK50H27
Signalling System 7
Link Controller
SECTION 1 - FEATURES
Complete Level 2 Implementation of SS7.
Compatible with 1988 CCITT, AT&T, ANSI,
and Bellcore Signalling System Number 7 link
level protocols.
Optional operation to comply with Japanese
TTC JT-Q703 specification requirements
Pin-for-pin and architecturally compatible with
MK50H25 (X.25/LAPD), MK50H29 (SDLC),
and MK50H28(Frame Relay).
System clock rates up to 33 MHz (MK50H27 -
33), or 25 MHz (MK50H27 - 25).
Data rate up to 4 Mbps continuous for SS7
protocol processing, 20 Mbps for transparent
HDLC mode, or up to 51 Mbps bursted
(gapped data clocks, non-continuous data).
On chip DMA control with programmable burst
length.
DMA transfer rate of up to 13.3 Mbytes/sec us-
ing optional 5 SYSCLK DMA cycle (150 nS) at
33 MHz SYSCLK.
Buffer Management includes:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
Selectable BEC or PCR retransmission meth-
ods, including forced retransmission for PCR.
Handles all 7 SS7 Timers, plus the additional
Signal Unit interval timers for Japanese SS7.
Handles all SS7 frame formatting:
- Zero bit insert and delete
- FCS generation and detection
- Frame delimiting with flags
Programmable minimum Signal Unit spacing
(number of flags between SU’s)
Handles all sequencing and link control.
Selectable FCS of 16 or 32 bits.
Testing Facilities:
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test.
Programmable for full or half duplex operation
Programmable Watchdog Timers for RCLK
and TCLK (to detect absence of data clocks)
September 1997
DIP48
PLCC 52
Available in 52 pin PLCC, 84 pin PLCC(for use
with external ROM), or 48 pin DIP packages.
SECTION 2 - INTRODUCTION
The SGS - Thomson SS7 Signalling Link Control-
ler (MK50H27) is a VLSI semiconductor device
which provides a complete level 2 data communi-
cation control conforming to the CCITT, ANSI,
BELLCORE, and AT&T versions of SS7, as well
as options to allow conformance to TTC JT-Q703
(Japanese SS7). This includes signal unit format-
ting, transparency (so-called ”bit-stuffing”), error
recovery by two types of retransmission, error
monitoring, sequence number control, link status
control, and fill in signal unit generation.
One of the outstanding features of the MK50H27
is its buffer management which includes on-chip
DMA. This feature allows users to handle multi-
ple MSU’s of receive and transmit data at a time.
(A conventional data link control chip plus a sepa-
rate DMA chip would handle data for only a single
block at a time.) The MK50H27 will move multiple
blocks of receive and transmit data directly into
1/56
MK50H27
INTRODUCTION (Continued)
and out of memory through the Host’s bus. A
possible system configuration for the MK50H27 is
shown in figure 1.
For added flexibility a transparent mode provides
an HDLC transport mechanism without link layer
support. In this mode no protocol processing is
done, all data received between opening flag and
CRC is written to the shared memory buffer and it
is up to the user to take care of the upper level
software.
The MK50H27 may be used with any of several
popular microprocessors, such as: 68040 ...
68000, 6800, Z8000, Z80, 80486 ... 8086, i960,
etc.
The MK50H27 may be operated in either full or
half duplex mode. In half duplex mode, the RTS
and CTS modem control pins are provided. In full
duplex mode, these pins become user program-
mable I/O pins. All signal pins on the MK50H27
are TTL compatible. This has the advantage of
making the MK50H27 independent of the physical
interface. As shown in figure 1, line drivers and
receivers are used for electrical connection to the
physical layer.
DIP48 PIN CONNECTION
(Top view)
VSS-GND
DAL07
DAL06
DAL05
DAL04
DAL03
DAL02
DAL01
DAL00
READ
INTR
DALI
DALO
DAS
BMO, BYTE, BUSREL
BMI, BUSAKO
HOLD, BUSRQ
ALE, AS
HLDA
CS
ADR
READY
RESET
VSS-GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
VCC (+5V)
DAL08
DAL09
DAL10
DAL11
DAL12
DAL13
DAL14
DAL15
A16
A17
A18
A19
A20
A21
A22
A23
RD
DSR, CTS
TD
SYSCLK
RCLK
DTR, RTS
TCLK
M
K
5
0
H
2
7
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2/56
MK50H27
PLCC52 PIN CONNECTION
(Top view)
DAL02
DAL01
DAL00
READ
INTR
DALI
DALO
DAS
BMO/BYTE/BUSREL
No Connect
BM1/BUSAKO
HOLD/BUSRQ
ALE/AS
8 7
No Connect
DAL03
DAL04
DAL05
DAL06
DAL07
VSS
VCC
DAL08
DAL09
DAL10
DAL11
DAL12
1 52
47 46
MK50H27Q
20
21
ADR
READY
RESET
VSS(GND)
No Connect
HLDA
CS
34
33
TCLK
DTR/RTS
RCLK
SYSCLK
TD
DSR/CTS
DAL13
DAL14
DAL15
A16
A17
A18
A19
A20
A21
A22
No Connect
A23
RD
3/56
MK50H27
TAble 1 - PIN DESCRIPTION
LEGEND:
I
Input only
IO
Input / Output
OD
Open Drain (no internal pull-up)
Note:
O
3S
Output only
3-State
Pin out for 52 pin PLCC is shown in brackets.
PIN(S)
2-9
40-47
[2-10
44-51]
10
[11]
TYPE
IO/3S
DESCRIPTION
The time multiplexed Data/Address bus. During the address portion of a
memory transfer, DAL<15:00> contains the lower 16 bits of the memory
address.
During the data portion of a memory transfer, DAL<15:00> contains the read
or write data, depending on the type of transfer.
READ indicates the type of operation that the bus controller is performing
during a bus transaction. READ is driven by the MK50H27 only while it is the
BUS MASTER. READ is valid during the entire bus transaction and is
tristated at all other times.
MK50H27 as a Bus Slave :
READ = HIGH - Data is placed on the DAL lines by the chip.
READ = LOW - Data is taken off the DAL lines by the chip.
MK50H27 as a Bus Master :
READ = HIGH - Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.
INTERRUPT is an attention interrupt line that indicates that one or more of
the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.
INTERRUPT is enabled by CSR0<09>, INEA=1.
DAL IN is an external bus transceiver control line. DALI is driven by the
MK50H27 only while it is the BUS MASTER. DALI is asserted by the
MK50H27 when it reads from the DAL lines during the data portion of a
READ transfer. DALI is not asserted during a WRITE transfer.
DAL OUT is an external bus transceiver control line. DALO is driven by the
MK50H27 only while it is the BUS MASTER. DALO is asserted by the
MK50H27 when it drives the DAL lines during the address portion of a READ
transfer or for the duration of a WRITE transfer.
DATA STROBE defines the data portion of a bus transaction. By definition,
data is stable and valid at the low to high transition of DAS. This signal is
driven by the MK50H27 while it is the BUS MASTER. During the BUS
SLAVE operation, this pin is used as an input. At all other times the signal is
tristated.
I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set
to a one, pin 15 becomes input BUSREL and is used by the host to signal
the MK50H27 to terminate a DMA burst after the current bus transfer has
completed. If bit 06 is clear then pin 15 is an output and behaves as
described below for pin 16.
Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON).
If CSR4<00> BCON = 0,
I/O PIN 15 = BMO (O/3S)
I/O PIN 16 = BM1 (O/3S)
BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK50H27 drives these lines only as a Bus
Master. MK50H27 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BM1
BM0
TYPE OF TRANSFER
LOW
LOW
ENTIRE WORD
LOW
HIGH
UPPER BYTE
(DAL<15:08>)
HIGH
LOW
LOWER BYTE
(DAL<07:00>)
HIGH
HIGH
NONE
SIGNAL NAME
DAL<15:00>
READ
IO/3S
INTR
11
[12]
12
[13]
O/OD
DALI
O/3S
DALO
13
[14]
O/3S
DAS
14
[15]
IO/3S
BMO
BYTE
BUSREL
15
[16]
IO/3S
BM1
BUSAKO
16
[18]
O/3S
4/56
MK50H27
Table 1: PIN DESCRIPTION
(continued)
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
If CSR4<00> BCON = 1,
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO (O)
Byte selection is done using the BYTE line and DAL<00> latched during the
address portion of the bus transaction. MK50H27 drives BYTE only as a Bus
Master and ignores it when a Bus Slave. Byte selection is done as outlined
in the following table.
BYTE
DAL<00>
TYPE OF TRANSFER
LOW
LOW
ENTIRE WORD
LOW
HIGH
ILLEGAL CONDITION
HIGH
LOW
LOWER BYTE
HIGH
HIGH
UPPER BYTE
BUSAKO is a bus request daisy chain output. If MK50H27 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK50H27 is
requesting the bus when it receives HLDA, BUSAKO will remain high
Note: All transfers are entire word unless the MK50H27 is configured for 8 bit
operation.
HOLD
BUSRQ
17
[19]
IO/OD
Pin 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
I/O PIN 17 = HOLD
HOLD request is asserted by MK50H27 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is
held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK50H27 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low
for the entire ensuing bus transaction.
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK50H27 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
I/O PIN 18 = ALE
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer. As ALE, the signal transitions from high
to low during the address portion of the transfer and remains low during the
data portion.
If CSR4<01> ACON = 1,
I/O PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus transfer.
The low to high transition of AS can be used by a slave device to strobe the
address into a register.
AS is effectively the inversion of ALE.
HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in
response to MK50H27’s assertion of HOLD, the MK50H27 is the Bus
Master. HLDA should be deasserted ONLY after HOLD has been released
by the MK50H27.
CHIP SELECT indicates, when low, that the MK50H27 is the slave device
for the data transfer. CS must be valid throughout the entire transaction.
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used by
the chip when CS is low.
ADR
PORT
LOW
REGISTER DATA PORT
HIGH
REGISTER ADDRESS PORT
When the MK50H27 is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ cycle.
ALE
AS
18
[20]
O/3S
HLDA
19
[21]
I
CS
ADR
20
[22]
21
[23]
I
I
READY
22
[24]
IO/OD
5/56
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